The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK
frequency combined with the MCLK division and the digital filter
decimation rates, determines the sampling frequency. Along with
MCLK_DIV, the power mode is also configured according to datasheet
recommendations.
From user space, available sampling frequencies can be read. However,
it is not required for an exact value to be entered, since the driver
will look for the closest available match.
When the device configuration changes (for example, if the filter
decimation rate changes), a SYNC_IN pulse is required.
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The ad7768-1 is a single channel, precision 24-bit analog to digital
converter (ADC).
This basic patch configures the device in fast mode, with 32 kSPS and
leaves the default sinc5 filter.
Two data conversion modes are made available. When data is retrieved by
using the read_raw attribute, one shot single conversion mode is set.
The continuous conversion mode is enabled when the triggered buffer
mechanism is used. To assure correct data retrieval, the driver waits
for the interrupt triggered by the low to high transition of the DRDY
pin.
Datasheets:
Link: https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Stefan Popa