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Автор SHA1 Сообщение Дата
Arnd Bergmann d319fc6dc1 Renesas ARM Based SoC r8a7745 SYSC Driver Updates for v4.10
* Add support for the r8a7745 SoC to rcar-sysc
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Merge tag 'renesas-r8a7745-sysc-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Pull "Renesas ARM Based SoC r8a7745 SYSC Driver Updates for v4.10" from Simon Horman:

* Add support for the r8a7745 SoC to rcar-sysc

* tag 'renesas-r8a7745-sysc-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  soc: renesas: rcar-sysc: add R8A7745 support
  ARM: shmobile: r8a7745: add power domain index macros

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30 16:39:48 +01:00
Arnd Bergmann 2aa488a6bc misc: sram: remove useless #ifdef
A recent patch added a new function that is now unused whenever
CONFIG_OF is disabled:

drivers/misc/sram.c:342:12: error: 'atmel_securam_wait' defined but not used [-Werror=unused-function]

There is actually no reason for the #ifdef, because the driver
currently cannot be used in a meaningful way without CONFIG_OF,
and there is no compile-time dependency.

Removing that #ifdef and the respective of_match_ptr() avoids the
warning and simplifies the driver slightly.

Fixes: 2ae2e28852 ("misc: sram: add Atmel securam support")
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30 15:43:25 +01:00
Arnd Bergmann 11128b9021 Fixes for drivers already queued to prevent
section mismatch warnings introduced by them.
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Merge tag 'davinci-for-v4.10/drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers

Pull "DaVinci driver updates for v4.10 (part 2)" from Sekhar Nori:

Fixes for drivers already queued to prevent
section mismatch warnings introduced by them.

* tag 'davinci-for-v4.10/drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name()
  bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name()
2016-11-30 14:58:00 +01:00
Thierry Reding d09a0011ec drivers: psci: Allow PSCI node to be disabled
Allow disabling PSCI support (mostly for testing purposes) by setting
the status property to "disabled". This makes the node behave in much
the same way as proper device nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-25 23:26:05 +01:00
Kevin Brodsky ea8b1c4a60 drivers: psci: PSCI checker module
On arm and arm64, PSCI is one of the possible firmware interfaces
used for power management. This includes both turning CPUs on and off,
and suspending them (entering idle states).

This patch adds a PSCI checker module that enables basic testing of
PSCI operations during startup. There are two main tests: CPU
hotplugging and suspending.

In the hotplug tests, the hotplug API is used to turn off and on again
all CPUs in the system, and then all CPUs in each cluster, checking
the consistency of the return codes.

In the suspend tests, a high-priority thread is created on each core
and uses low-level cpuidle functionalities to enter suspend, in all
the possible states and multiple times. This should allow a maximum
number of CPUs to enter the same sleep state at the same or slightly
different time.

In essence, the suspend tests use a principle similar to that of the
intel_powerclamp driver (drivers/thermal/intel_powerclamp.c), but the
threads are only kept for the duration of the test (they are already
gone when userspace is started) and it does not require to stop/start
the tick.

While in theory power management PSCI functions (CPU_{ON,OFF,SUSPEND})
could be directly called, this proved too difficult as it would imply
the duplication of all the logic used by the kernel to allow for a
clean shutdown/bringup/suspend of the CPU (the deepest sleep states
implying potentially the shutdown of the CPU).

Note that this file cannot be compiled as a loadable module, since it
uses a number of non-exported identifiers (essentially for
PSCI-specific checks and direct use of cpuidle) and relies on the
absence of userspace to avoid races when calling hotplug and cpuidle
functions.

For now at least, CONFIG_PSCI_CHECKER is mutually exclusive with
CONFIG_TORTURE_TEST, because torture tests may also use hotplug and
cause false positives in the hotplug tests.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kevin Hilman <khilman@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> [torture test config]
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
[lpieralisi: added cpuidle locking, reworded commit log/kconfig entry]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-25 23:25:52 +01:00
Bartosz Golaszewski d0c7546f62 memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name()
In order to avoid a section mismatch drop the call to
of_flat_dt_get_machine_name() when printing the error message.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-11-23 20:26:42 +05:30
Bartosz Golaszewski 48c2833738 bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name()
In order to avoid a section mismatch drop the call to
of_flat_dt_get_machine_name() when printing the error message.

While we're at it: fix a typo.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-11-23 20:26:42 +05:30
Sergei Shtylyov 141723e0cb soc: renesas: rcar-sysc: add R8A7745 support
Add support for RZ/G1E (R8A7745) SoC power areas to the R-Car SYSC driver.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-23 14:28:41 +01:00
Sergei Shtylyov 97ca840299 ARM: shmobile: r8a7745: add power domain index macros
Add macros usable by the device tree sources to reference R8A7745 SYSC power
domains by index.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-23 14:06:21 +01:00
Olof Johansson b029ffe00c soc: tegra: Core SoC changes for v4.10-rc1
This contains mostly cleanup and new feature work on the power
 management controller as well as the addition of a Kconfig symbol for
 the new Tegra186 (Parker) SoC generation.
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Merge tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

soc: tegra: Core SoC changes for v4.10-rc1

This contains mostly cleanup and new feature work on the power
management controller as well as the addition of a Kconfig symbol for
the new Tegra186 (Parker) SoC generation.

* tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Use consistent naming for PM domains
  soc/tegra: pmc: Remove genpd when adding provider fails
  soc/tegra: pmc: Check return code for pm_genpd_init()
  soc/tegra: pmc: Clean-up I/O rail error messages
  soc/tegra: pmc: Simplify IO rail bit handling
  soc/tegra: pmc: Guard against uninitialised PMC clock
  soc/tegra: pmc: Add I/O pad voltage support
  soc/tegra: pmc: Use consistent ordering of bit definitions
  soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()
  soc/tegra: pmc: Use BIT macro for register field definition

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:42:33 -08:00
Olof Johansson 84f1f0c199 bus: Add Tegra GMI support
This provides a driver to enable the use of the Generic Memory Interface
 found on Tegra SoCs that can host various types of high-speed devices.
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Merge tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

bus: Add Tegra GMI support

This provides a driver to enable the use of the Generic Memory Interface
found on Tegra SoCs that can host various types of high-speed devices.

* tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  bus: Add support for Tegra Generic Memory Interface
  dt/bindings: Add bindings for Tegra GMI controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:32:57 -08:00
Olof Johansson 857ff3fddc reset: Add Tegra BPMP reset driver
This contains a patch which implements a reset driver using the services
 provided by the BPMP firmware (via the MRQ_RESET request).
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Merge tag 'tegra-for-4.10-reset' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

reset: Add Tegra BPMP reset driver

This contains a patch which implements a reset driver using the services
provided by the BPMP firmware (via the MRQ_RESET request).

* tag 'tegra-for-4.10-reset' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  reset: Add Tegra BPMP reset driver

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:31:56 -08:00
Olof Johansson e40719dd01 firmware: Add Tegra IVC and BPMP support
IVC is an inter-processor communication protocol that uses shared memory
 to exchange data between processors. The BPMP driver makes use of this
 to communicate with the Boot and Power Management Processor (BPMP) and
 uses an additional hardware synchronization primitive from the HSP block
 to signal availability of new data (doorbell).
 
 Firmware running on the BPMP implements a number of services such as the
 control of clocks and resets within the system, or the ability to ungate
 or gate power partitions.
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Merge tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

firmware: Add Tegra IVC and BPMP support

IVC is an inter-processor communication protocol that uses shared memory
to exchange data between processors. The BPMP driver makes use of this
to communicate with the Boot and Power Management Processor (BPMP) and
uses an additional hardware synchronization primitive from the HSP block
to signal availability of new data (doorbell).

Firmware running on the BPMP implements a number of services such as the
control of clocks and resets within the system, or the ability to ungate
or gate power partitions.

* tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
  dt-bindings: Add power domains to Tegra BPMP firmware
  firmware: tegra: Add BPMP support
  firmware: tegra: Add IVC library
  dt-bindings: firmware: Add bindings for Tegra BPMP

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:28:14 -08:00
Olof Johansson dd3eedd338 mailbox: Add Tegra HSP driver
This contains the device tree bindings and a driver for the Tegra HSP, a
 hardware block that provides hardware synchronization primitives and is
 the foundation for inter-processor communication between CPU and BPMP.
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Merge tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

mailbox: Add Tegra HSP driver

This contains the device tree bindings and a driver for the Tegra HSP, a
hardware block that provides hardware synchronization primitives and is
the foundation for inter-processor communication between CPU and BPMP.

* tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
  mailbox: Add Tegra HSP driver
  dt-bindings: mailbox: Add Tegra HSP binding
  soc/tegra: Add Tegra186 support

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:23:06 -08:00
Olof Johansson 78d375b97e Reset controller changes for v4.10
- remove obsolete STiH41[56] platform support
 - add Oxford Semiconductor OX820 support
 - add reset index include files for OX810SE and OX820
 - make drivers with boolean Kconfig options explicitly
   non-modular
 - allow shared pulsed resets via reset_control_reset, which
   in this case means that the reset must have been triggered
   once, but possibly earlier, after the function returns, and
   is never triggered again for the lifetime of the reset
   control
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Merge tag 'reset-for-4.10' of git://git.pengutronix.de/git/pza/linux into next/drivers

Reset controller changes for v4.10

- remove obsolete STiH41[56] platform support
- add Oxford Semiconductor OX820 support
- add reset index include files for OX810SE and OX820
- make drivers with boolean Kconfig options explicitly
  non-modular
- allow shared pulsed resets via reset_control_reset, which
  in this case means that the reset must have been triggered
  once, but possibly earlier, after the function returns, and
  is never triggered again for the lifetime of the reset
  control

* tag 'reset-for-4.10' of git://git.pengutronix.de/git/pza/linux:
  reset: allow using reset_control_reset with shared reset
  reset: lpc18xx: make it explicitly non-modular
  reset: zynq: make it explicitly non-modular
  reset: sunxi: make it explicitly non-modular
  reset: socfpga: make it explicitly non-modular
  reset: berlin: make it explicitly non-modular
  dt-bindings: reset: oxnas: Update for OX820
  dt-bindings: reset: oxnas: Add include file with reset indexes
  reset: oxnas: Add OX820 support
  reset: sti: softreset: Remove obsolete platforms from dt binding doc.
  reset: sti: Remove STiH415/6 reset support

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 16:17:45 -08:00
Olof Johansson 555b2b5d25 Drivers for 4.10:
- few fixes for the memory drivers
  - minimal security module driver
  - support for the Secure SRAM
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Merge tag 'at91-ab-4.10-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/drivers

Drivers for 4.10:

 - few fixes for the memory drivers
 - minimal security module driver
 - support for the Secure SRAM

* tag 'at91-ab-4.10-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
  misc: sram: add Atmel securam support
  misc: sram: document new compatible
  ARM: at91: add secumod register definitions
  Documentation: dt: atmel-at91: Document secumod bindings
  memory: atmel-sdramc: use builtin_platform_driver to simplify the code
  memory: atmel-ebi: fix return value check in at91_ebi_dev_disable()

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 09:53:55 -08:00
Thierry Reding dc606c5205 reset: Add Tegra BPMP reset driver
This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:34:56 +01:00
Thierry Reding 801fc02214 Merge branch 'for-4.10/firmware' into for-4.10/reset 2016-11-18 14:34:46 +01:00
Stephen Warren b704ed8095 dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
The BPMP implements some services which must be represented by separate
nodes. For example, it can provide access to certain I2C controllers,
and the I2C bindings represent each I2C controller as a device tree
node. Update the binding to describe how the BPMP supports this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: renamed bpmp-i2c to i2c as per Rob]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:44 +01:00
Stephen Warren ad7cb19824 dt-bindings: Add power domains to Tegra BPMP firmware
The Tegra186 BPMP is also a provider of power domains. Enhance the
device tree binding to describe this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:43 +01:00
Thierry Reding 983de5f971 firmware: tegra: Add BPMP support
The Boot and Power Management Processor (BPMP) is a co-processor found
on Tegra SoCs. It is designed to handle the early stages of the boot
process and offload power management tasks (such as clocks, resets,
powergates, ...) as well as system control services.

Compared to the ARM SCPI, the services provided by BPMP are message-
based rather than method-based. The BPMP firmware driver provides the
services to transmit data to and receive data from the BPMP. Users can
also register a Message ReQuest (MRQ), for which a service routine will
be run when a corresponding event is received from the firmware.

A set of messages, called the BPMP ABI, are specified for a number of
different services provided by the BPMP (such as clocks or resets).

Based on work by Sivaram Nair <sivaramn@nvidia.com> and Joseph Lo
<josephl@nvidia.com>.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:43 +01:00
Thierry Reding ca791d7f42 firmware: tegra: Add IVC library
The Inter-VM communication (IVC) is a communication protocol which is
designed for interprocessor communication (IPC) or the communication
between the hypervisor and the virtual machine with a guest OS.

Message channels are used to communicate between processors. They are
backed by DRAM or SRAM, so care must be taken to maintain coherence of
data.

The IVC library maintains memory-based descriptors for the transmission
and reception channels as well as the data coherence of the counter and
payload. Clients, such as the driver for the BPMP firmware, can use the
library to exchange messages with remote processors.

Based on work by Peter Newman <pnewman@nvidia.com> and Joseph Lo
<josephl@nvidia.com>.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:42 +01:00
Joseph Lo d55865608f dt-bindings: firmware: Add bindings for Tegra BPMP
The Boot and Power Management Processor (BPMP) is a co-processor found
in Tegra SoCs. It is designed to handle the early stages of the boot
process as well as to offload power management tasks (such as clocks,
resets, powergates, ...).

The binding document defines the resources that are used by the BPMP
firmware, which implements the interprocessor communication (IPC)
between the CPU and the BPMP.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:41 +01:00
Thierry Reding 3dc8367499 Merge branch 'for-4.10/mailbox' into for-4.10/firmware 2016-11-18 14:33:29 +01:00
Dan Carpenter 68050eb6c6 mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
We have to use the _safe version of list_for_each() because we're
freeing the pointer as we go along.  (This might not show up testing
depending on what config options you have enabled).

Fixes: 0fe88461a0 ("mailbox: Add Tegra HSP driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:32:13 +01:00
Thierry Reding 0fe88461a0 mailbox: Add Tegra HSP driver
This driver exposes a mailbox interface for interprocessor communication
using the Hardware Synchronization Primitives (HSP) module's doorbell
mechanism. There are multiple HSP instances and they provide additional
features such as shared mailboxes, shared and arbitrated semaphores.

A driver for a remote processor can use the mailbox client provided by
the HSP driver and build an IPC protocol on top of this synchronization
mechanism.

Based on work by Joseph Lo <josephl@nvidia.com>.

Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:26:13 +01:00
Olof Johansson e87c077ff6 - prepare mtk-scpsys to for multi soc support
- add support for mt2701 to mtk-scpsys
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Merge tag 'v4.9-next-soc' of https://github.com/mbgg/linux-mediatek into next/drivers

- prepare mtk-scpsys to for multi soc support
- add support for mt2701 to mtk-scpsys

* tag 'v4.9-next-soc' of https://github.com/mbgg/linux-mediatek:
  soc: mediatek: Add MT2701 scpsys driver
  soc: mediatek: Refine scpsys to support multiple platform

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17 23:46:51 -08:00
Olof Johansson b9bccf35ac This pull request adds two new drivers for better
support for LCD found on DaVinci DA8xx devices.
 
 They allow configuration of memory interface and
 bus priorities on the SoC to allow sufficient
 bandwidth for the LCD and prevent underruns.
 
 The DT bindings have been reviewed by Rob and
 patches have been reviewed by Kevin.
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Merge tag 'davinci-for-v4.10/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers

This pull request adds two new drivers for better
support for LCD found on DaVinci DA8xx devices.

They allow configuration of memory interface and
bus priorities on the SoC to allow sufficient
bandwidth for the LCD and prevent underruns.

The DT bindings have been reviewed by Rob and
patches have been reviewed by Kevin.

* tag 'davinci-for-v4.10/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  bus: davinci: add support for da8xx bus master priority control
  memory: davinci: add support for da8xx DDR2/mDDR controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17 23:44:43 -08:00
Olof Johansson 5589d62484 Qualcomm ARM Based Driver Updates for v4.10
* Fixup QCOM SCM to use devm_reset_controller_register
 * Add QCOM pinctrl to Qualcomm MAINTAINERS entry
 * Add PM8994 regulator definitions
 * Add stub for WCNSS_CTRL API
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Merge tag 'qcom-drivers-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers

Qualcomm ARM Based Driver Updates for v4.10

* Fixup QCOM SCM to use devm_reset_controller_register
* Add QCOM pinctrl to Qualcomm MAINTAINERS entry
* Add PM8994 regulator definitions
* Add stub for WCNSS_CTRL API

* tag 'qcom-drivers-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  firmware: qcom: scm: Use devm_reset_controller_register()
  MAINTAINERS: add drivers/pinctrl/qcom to ARM/QUALCOMM SUPPORT
  pinctrl: pm8994: add pad voltage regulator defines
  soc: qcom: wcnss_ctrl: Stub wcnss_ctrl API

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17 23:38:27 -08:00
Olof Johansson 7558341659 Changes to the power-domain driver including counter presets now being set
by firmware on the rk3399, avoiding infite loops when powering on/off a
 domain and actually returning an error if power-domain addition fails.
 The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove
 functionality as well.
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Merge tag 'v4.10-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers

Changes to the power-domain driver including counter presets now being set
by firmware on the rk3399, avoiding infite loops when powering on/off a
domain and actually returning an error if power-domain addition fails.
The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove
functionality as well.

* tag 'v4.10-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell
  soc: rockchip: power-domain: use pm_genpd_remove in error cleanup
  soc: rockchip: power-domain: avoid infinite loop
  soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17 23:31:18 -08:00
Mirza Krak 40eb477678 bus: Add support for Tegra Generic Memory Interface
The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...

Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: symmetry and coding style OCD]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 17:27:53 +01:00
Mirza Krak 1de9aecbb0 dt/bindings: Add bindings for Tegra GMI controller
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.

Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 17:27:52 +01:00
Joseph Lo e983940270 dt-bindings: mailbox: Add Tegra HSP binding
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
with one another. A set of hardware synchronization primitives for
interprocessor communication (IPC) is provided. IPC protocols can use
use these hardware synchronization primitives when operating between
processors in an AMP configuration.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:52:58 +01:00
Thierry Reding 15326c1ad8 Merge branch 'for-4.10/soc' into for-4.10/mailbox 2016-11-15 15:52:35 +01:00
Thierry Reding 4522112069 soc/tegra: pmc: Use consistent naming for PM domains
The various error messages refer to the PM domains as "power domain",
"genpd" and "PM domain". That's confusing, so convert all error messages
to use the most prominent: "PM domain".

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:56 +01:00
Jon Hunter 0b137340d0 soc/tegra: pmc: Remove genpd when adding provider fails
Commit 3fe577107c ("PM / Domains: Add support for removing PM
domains") add support for removing PM domains. Update the Tegra PMC
driver to remove PM domains if we fail to add a provider for the PM
domain.

Please note that the code under 'power_on_cleanup' label does not
really belong in the clean-up error path for tegra_powergate_add().
To keep the error path simple, remove this label and move the
associated code to where it needs to be invoked.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:55 +01:00
Jon Hunter cd5ceda27d soc/tegra: pmc: Check return code for pm_genpd_init()
Commit 7eb231c337 ("PM / Domains: Convert pm_genpd_init() to return
an error code") updated pm_genpd_init() to return an error code. Update
the Tegra PMC driver to check the return value from pm_genpd_init() and
handle any errors returned.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: use pr_err() instead of dev_err()]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:54 +01:00
Thierry Reding 54e247211f soc/tegra: pmc: Clean-up I/O rail error messages
Use pr_err() instead of dev_err() when the pmc->dev field has not been
initialized yet and add a few missing error messages as well as remove
duplicate ones.

Based on work by Jon Hunter <jonathanh@nvidia.com>.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:53 +01:00
Jon Hunter 27b12b4e58 soc/tegra: pmc: Simplify IO rail bit handling
The function tegra_io_rail_prepare() converts the IO rail ID into a
bit position that is used to check the status and control the IO rail
in the PMC registers. However, rather than converting to a bit position
it is more useful to convert to a bit-mask because this is what is
actually used. By doing so the BIT() marco only needs to be used once
and we can use the IO_DPD_REQ_CODE_MASK when checking for erroneous rail
IDs.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: rebase and rename bit -> mask]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:53 +01:00
Jon Hunter f4392d6da5 soc/tegra: pmc: Guard against uninitialised PMC clock
It is possible for the public functions, tegra_io_rail_power_on/off()
to be called before the PMC device has been probed. If this happens
then the pmc->clk member will not be initialised and the call to
clk_get_rate() in tegra_io_rail_prepare() will return zero and lead
to a divide-by-zero exception. The function clk_get_rate() will return
zero if a NULl clk pointer is passed. Therefore, rather that checking
if pmc->clk is initialised, fix this by checking the return value for
clk_get_rate() to make sure it is not zero.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:52 +01:00
Laxman Dewangan 21b4991051 soc/tegra: pmc: Add I/O pad voltage support
I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such
pad can be used to control the common voltage signal level and power
state of the pins in the given pad.

I/O pads can be powered down even if the system is active, which can
save power from that I/O interface. For SoC generations prior to
Tegra124 the I/O pad voltage is automatically detected and hence the
system software doesn't need to configure it. However, starting with
Tegra210 the detection logic has been removed, so explicit control of
the I/O pad voltage by system software is required.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:51 +01:00
Thierry Reding 95b780b3d7 soc/tegra: pmc: Use consistent ordering of bit definitions
Bit definitions are sorted in decreasing order by offset. Apply the same
ordering to all definitions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:51 +01:00
Laxman Dewangan 84cf85ea6e soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()
The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:50 +01:00
Laxman Dewangan 6c0bd217c3 soc/tegra: pmc: Use BIT macro for register field definition
Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:51:49 +01:00
Joseph Lo 25a0644265 soc/tegra: Add Tegra186 support
The Tegra186 features a combination of Denver and Cortex-A57 CPU cores
and a GPU based on the Pascal architecture. It contains an ADSP with a
Cortex-A9 CPU used for audio processing, hardware video encoders and
decoders with multi-format support, ISP for image capture processing
and BPMP for power management.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 15:50:50 +01:00
Bartosz Golaszewski 8e7223fc86 bus: davinci: add support for da8xx bus master priority control
Create the driver for the da8xx master peripheral priority
configuration and implement support for writing to the three
Master Priority registers on da850 SoCs.

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-11-14 17:20:29 +05:30
Bartosz Golaszewski 62a8a73923 memory: davinci: add support for da8xx DDR2/mDDR controller
Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-11-14 17:18:34 +05:30
Martin Blumenstingl 7da33a37b4 reset: allow using reset_control_reset with shared reset
Some SoCs (for example Amlogic GXBB) implement a reset controller which
only supports a reset pulse (triggered via reset_control_reset). At the
same time multiple devices (in case of the Amlogic GXBB SoC both USB
PHYs) are sharing the same reset line.

This patch allows using reset_control_reset also for shared resets.
There are limitations though:
reset_control_reset can only be used if reset_control_assert was not
used yet.
reset_control_assert can only be used if reset_control_reset was not
used yet.
For shared resets the reset is only triggered once for the lifetime of
the reset_control instance (the reset can be triggered again if all
consumers of that specific reset_control are gone, as the reset
framework will free the reset_control instance in that case).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-11-14 09:58:28 +01:00
Wei Yongjun bd4760ca03 firmware: qcom: scm: Use devm_reset_controller_register()
Use devm_reset_controller_register() for the reset controller
registration and fixes the memory leak when unload the module.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-11-12 23:24:51 -06:00
Michael Scott 4fb1a42078 MAINTAINERS: add drivers/pinctrl/qcom to ARM/QUALCOMM SUPPORT
When running checkpatch.pl on a new pinctrl driver in
drivers/pinctrl/qcom, I noticed a warning about creating
a new maintainer.  The drivers/pinctrl/qcom folder doesn't have
anyone assigned in the MAINTAINERS file.

Let's assign it to ARM/QUALCOMM SUPPORT.

Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-11-12 23:24:50 -06:00