Jerome Brunet d6ee1e7e90 clk: meson: axg: mark fdiv2 and fdiv3 as critical ... Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor uses the fdiv2 and fdiv3 to, among other things, provide the cpu clock. Until clock hand-off mechanism makes its way to CCF and the generic SCPI claims platform specific clocks, these clocks must be marked as critical to make sure they are never disabled when needed by the co-processor. Fixes: 05f814402d ("clk: meson: add fdiv clock gates") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2018-11-08 10:21:21 -08:00
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Kconfig	clk: meson: axg: add the audio clock controller driver	2018-07-09 13:48:26 +02:00
Makefile	clk: meson: remove unused clk-audio-divider driver	2018-07-09 13:48:59 +02:00
axg-aoclk.c	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
axg-aoclk.h	clk: meson-axg: Add AO Clock and Reset controller driver	2018-05-15 14:19:43 +02:00
axg-audio.c	clk: meson: axg: round audio system master clocks down	2018-09-26 12:02:00 +02:00
axg-audio.h	clk: meson: axg: add the audio clock controller driver	2018-07-09 13:48:26 +02:00
axg.c	clk: meson: axg: mark fdiv2 and fdiv3 as critical	2018-11-08 10:21:21 -08:00
axg.h	clk: meson: clk-pll: remove od parameters	2018-09-26 12:01:57 +02:00
clk-mpll.c	clk: meson: mpll: add round closest support	2018-05-21 11:31:29 +02:00
clk-phase.c	clk: meson: add clk-phase clock driver	2018-07-09 13:47:22 +02:00
clk-pll.c	clk: meson: clk-pll: drop hard-coded rates from pll tables	2018-09-26 12:02:00 +02:00
clk-regmap.c	This time we have a good set of changes to the core framework that do some	2018-06-09 12:06:24 -07:00
clk-regmap.h	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
clk-triphase.c	clk: meson: add triple phase clock driver	2018-07-09 13:47:22 +02:00
clkc-audio.h	clk: meson: add axg audio sclk divider driver	2018-07-09 13:48:25 +02:00
clkc.h	clk: meson: clk-pll: drop hard-coded rates from pll tables	2018-09-26 12:02:00 +02:00
gxbb-aoclk-32k.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
gxbb-aoclk.c	clk: meson: use SPDX license identifiers consistently	2018-05-18 12:08:29 +02:00
gxbb-aoclk.h	This time we have a good set of changes to the core framework that do some	2018-06-09 12:06:24 -07:00
gxbb.c	clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL	2018-11-08 10:12:46 -08:00
gxbb.h	clk: meson: clk-pll: remove od parameters	2018-09-26 12:01:57 +02:00
meson-aoclk.c	clk: meson: aoclk: refactor common code into dedicated file	2018-05-15 14:19:42 +02:00
meson-aoclk.h	clk: meson: aoclk: refactor common code into dedicated file	2018-05-15 14:19:42 +02:00
meson8b.c	clk: meson: meson8b: use the regmap in the internal reset controller	2018-09-26 12:02:00 +02:00
meson8b.h	clk: meson: clk-pll: remove od parameters	2018-09-26 12:01:57 +02:00
sclk-div.c	clk: meson: add axg audio sclk divider driver	2018-07-09 13:48:25 +02:00