343 строки
11 KiB
C
343 строки
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012-2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/kprobes.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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/*
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* Non-VHE: Both host and guest must save everything.
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*
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* VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and pstate,
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* which are handled as part of the el2 return state) on every switch.
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* tpidr_el0 and tpidrro_el0 only need to be switched when going
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* to host userspace or a different VCPU. EL1 registers only need to be
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* switched when potentially going to run a different VCPU. The latter two
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* classes are handled as part of kvm_arch_vcpu_load and kvm_arch_vcpu_put.
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*/
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static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
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{
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ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1);
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/*
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* The host arm64 Linux uses sp_el0 to point to 'current' and it must
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* therefore be saved/restored on every entry/exit to/from the guest.
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*/
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ctxt->gp_regs.regs.sp = read_sysreg(sp_el0);
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}
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static void __hyp_text __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
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{
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ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0);
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ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0);
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}
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static void __hyp_text __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
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{
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ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
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ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(SYS_SCTLR);
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ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
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ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(SYS_CPACR);
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ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(SYS_TTBR0);
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ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(SYS_TTBR1);
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ctxt->sys_regs[TCR_EL1] = read_sysreg_el1(SYS_TCR);
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ctxt->sys_regs[ESR_EL1] = read_sysreg_el1(SYS_ESR);
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ctxt->sys_regs[AFSR0_EL1] = read_sysreg_el1(SYS_AFSR0);
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ctxt->sys_regs[AFSR1_EL1] = read_sysreg_el1(SYS_AFSR1);
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ctxt->sys_regs[FAR_EL1] = read_sysreg_el1(SYS_FAR);
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ctxt->sys_regs[MAIR_EL1] = read_sysreg_el1(SYS_MAIR);
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ctxt->sys_regs[VBAR_EL1] = read_sysreg_el1(SYS_VBAR);
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ctxt->sys_regs[CONTEXTIDR_EL1] = read_sysreg_el1(SYS_CONTEXTIDR);
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ctxt->sys_regs[AMAIR_EL1] = read_sysreg_el1(SYS_AMAIR);
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ctxt->sys_regs[CNTKCTL_EL1] = read_sysreg_el1(SYS_CNTKCTL);
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ctxt->sys_regs[PAR_EL1] = read_sysreg(par_el1);
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ctxt->sys_regs[TPIDR_EL1] = read_sysreg(tpidr_el1);
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ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1);
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ctxt->gp_regs.elr_el1 = read_sysreg_el1(SYS_ELR);
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ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(SYS_SPSR);
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}
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static void __hyp_text __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
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{
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ctxt->gp_regs.regs.pc = read_sysreg_el2(SYS_ELR);
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ctxt->gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
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if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
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ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
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}
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void __hyp_text __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_save_el1_state(ctxt);
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__sysreg_save_common_state(ctxt);
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__sysreg_save_user_state(ctxt);
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__sysreg_save_el2_return_state(ctxt);
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}
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void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_save_common_state(ctxt);
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}
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NOKPROBE_SYMBOL(sysreg_save_host_state_vhe);
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void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_save_common_state(ctxt);
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__sysreg_save_el2_return_state(ctxt);
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}
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NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe);
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static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1);
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/*
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* The host arm64 Linux uses sp_el0 to point to 'current' and it must
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* therefore be saved/restored on every entry/exit to/from the guest.
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*/
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write_sysreg(ctxt->gp_regs.regs.sp, sp_el0);
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}
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static void __hyp_text __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
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write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
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}
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static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
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write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
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if (!cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
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write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
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write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
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} else if (!ctxt->__hyp_running_vcpu) {
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/*
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* Must only be done for guest registers, hence the context
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* test. We're coming from the host, so SCTLR.M is already
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* set. Pairs with __activate_traps_nvhe().
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*/
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write_sysreg_el1((ctxt->sys_regs[TCR_EL1] |
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TCR_EPD1_MASK | TCR_EPD0_MASK),
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SYS_TCR);
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isb();
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}
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write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
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write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], SYS_CPACR);
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write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], SYS_TTBR0);
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write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], SYS_TTBR1);
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write_sysreg_el1(ctxt->sys_regs[ESR_EL1], SYS_ESR);
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write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1], SYS_AFSR0);
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write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1], SYS_AFSR1);
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write_sysreg_el1(ctxt->sys_regs[FAR_EL1], SYS_FAR);
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write_sysreg_el1(ctxt->sys_regs[MAIR_EL1], SYS_MAIR);
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write_sysreg_el1(ctxt->sys_regs[VBAR_EL1], SYS_VBAR);
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write_sysreg_el1(ctxt->sys_regs[CONTEXTIDR_EL1],SYS_CONTEXTIDR);
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write_sysreg_el1(ctxt->sys_regs[AMAIR_EL1], SYS_AMAIR);
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write_sysreg_el1(ctxt->sys_regs[CNTKCTL_EL1], SYS_CNTKCTL);
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write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1);
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write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1);
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if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE) &&
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ctxt->__hyp_running_vcpu) {
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/*
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* Must only be done for host registers, hence the context
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* test. Pairs with __deactivate_traps_nvhe().
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*/
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isb();
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/*
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* At this stage, and thanks to the above isb(), S2 is
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* deconfigured and disabled. We can now restore the host's
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* S1 configuration: SCTLR, and only then TCR.
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*/
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write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
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isb();
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write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
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}
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write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
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write_sysreg_el1(ctxt->gp_regs.elr_el1, SYS_ELR);
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write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],SYS_SPSR);
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}
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static void __hyp_text
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__sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
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{
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u64 pstate = ctxt->gp_regs.regs.pstate;
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u64 mode = pstate & PSR_AA32_MODE_MASK;
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/*
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* Safety check to ensure we're setting the CPU up to enter the guest
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* in a less privileged mode.
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*
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* If we are attempting a return to EL2 or higher in AArch64 state,
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* program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
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* we'll take an illegal exception state exception immediately after
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* the ERET to the guest. Attempts to return to AArch32 Hyp will
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* result in an illegal exception return because EL2's execution state
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* is determined by SCR_EL3.RW.
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*/
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if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
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pstate = PSR_MODE_EL2h | PSR_IL_BIT;
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write_sysreg_el2(ctxt->gp_regs.regs.pc, SYS_ELR);
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write_sysreg_el2(pstate, SYS_SPSR);
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if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
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write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
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}
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void __hyp_text __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_restore_el1_state(ctxt);
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__sysreg_restore_common_state(ctxt);
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__sysreg_restore_user_state(ctxt);
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__sysreg_restore_el2_return_state(ctxt);
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}
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void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_restore_common_state(ctxt);
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}
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NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe);
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void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
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{
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__sysreg_restore_common_state(ctxt);
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__sysreg_restore_el2_return_state(ctxt);
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}
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NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
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void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
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{
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u64 *spsr, *sysreg;
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if (!vcpu_el1_is_32bit(vcpu))
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return;
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spsr = vcpu->arch.ctxt.gp_regs.spsr;
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sysreg = vcpu->arch.ctxt.sys_regs;
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spsr[KVM_SPSR_ABT] = read_sysreg(spsr_abt);
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spsr[KVM_SPSR_UND] = read_sysreg(spsr_und);
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spsr[KVM_SPSR_IRQ] = read_sysreg(spsr_irq);
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spsr[KVM_SPSR_FIQ] = read_sysreg(spsr_fiq);
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sysreg[DACR32_EL2] = read_sysreg(dacr32_el2);
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sysreg[IFSR32_EL2] = read_sysreg(ifsr32_el2);
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if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
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sysreg[DBGVCR32_EL2] = read_sysreg(dbgvcr32_el2);
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}
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void __hyp_text __sysreg32_restore_state(struct kvm_vcpu *vcpu)
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{
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u64 *spsr, *sysreg;
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if (!vcpu_el1_is_32bit(vcpu))
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return;
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spsr = vcpu->arch.ctxt.gp_regs.spsr;
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sysreg = vcpu->arch.ctxt.sys_regs;
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write_sysreg(spsr[KVM_SPSR_ABT], spsr_abt);
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write_sysreg(spsr[KVM_SPSR_UND], spsr_und);
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write_sysreg(spsr[KVM_SPSR_IRQ], spsr_irq);
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write_sysreg(spsr[KVM_SPSR_FIQ], spsr_fiq);
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write_sysreg(sysreg[DACR32_EL2], dacr32_el2);
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write_sysreg(sysreg[IFSR32_EL2], ifsr32_el2);
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if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
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write_sysreg(sysreg[DBGVCR32_EL2], dbgvcr32_el2);
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}
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/**
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* kvm_vcpu_load_sysregs - Load guest system registers to the physical CPU
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*
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* @vcpu: The VCPU pointer
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*
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* Load system registers that do not affect the host's execution, for
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* example EL1 system registers on a VHE system where the host kernel
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* runs at EL2. This function is called from KVM's vcpu_load() function
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* and loading system register state early avoids having to load them on
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* every entry to the VM.
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*/
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void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
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struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
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if (!has_vhe())
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return;
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__sysreg_save_user_state(host_ctxt);
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/*
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* Load guest EL1 and user state
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*
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* We must restore the 32-bit state before the sysregs, thanks
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* to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
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*/
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__sysreg32_restore_state(vcpu);
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__sysreg_restore_user_state(guest_ctxt);
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__sysreg_restore_el1_state(guest_ctxt);
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vcpu->arch.sysregs_loaded_on_cpu = true;
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activate_traps_vhe_load(vcpu);
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}
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/**
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* kvm_vcpu_put_sysregs - Restore host system registers to the physical CPU
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*
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* @vcpu: The VCPU pointer
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*
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* Save guest system registers that do not affect the host's execution, for
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* example EL1 system registers on a VHE system where the host kernel
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* runs at EL2. This function is called from KVM's vcpu_put() function
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* and deferring saving system register state until we're no longer running the
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* VCPU avoids having to save them on every exit from the VM.
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*/
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void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
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struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
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if (!has_vhe())
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return;
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deactivate_traps_vhe_put();
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__sysreg_save_el1_state(guest_ctxt);
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__sysreg_save_user_state(guest_ctxt);
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__sysreg32_save_state(vcpu);
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/* Restore host user state */
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__sysreg_restore_user_state(host_ctxt);
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vcpu->arch.sysregs_loaded_on_cpu = false;
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}
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void __hyp_text __kvm_enable_ssbs(void)
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{
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u64 tmp;
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asm volatile(
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"mrs %0, sctlr_el2\n"
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"orr %0, %0, %1\n"
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"msr sctlr_el2, %0"
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: "=&r" (tmp) : "L" (SCTLR_ELx_DSSBS));
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}
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