WSL2-Linux-Kernel/drivers/clk/zynq
Soren Brinkmann 765b7d4c4c clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes
Zynq's Ethernet clocks are created by the following hierarchy:
	mux0 ---> div0 ---> div1 ---> mux1 ---> gate
Rate change requests on the gate have to propagate all the way up to
div0 to properly leverage all dividers. Mux1 was missing the
CLK_SET_RATE_PARENT flag, which is required to achieve this.

This does not fix a specific regression but the clock driver was merged
for 3.11-rc1, so best to fix the known bugs before the release.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added to changelog]
2013-08-13 10:01:55 -07:00
..
Makefile arm: zynq: Migrate platform to clock controller 2013-05-27 09:21:22 +02:00
clkc.c clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes 2013-08-13 10:01:55 -07:00
pll.c clk: zynq: Factor out PLL driver 2013-05-21 16:21:35 +02:00