Will Deacon 679db70801 arm64: entry: Place an SB sequence following an ERET instruction ... Some CPUs can speculate past an ERET instruction and potentially perform speculative accesses to memory before processing the exception return. Since the register state is often controlled by a lower privilege level at the point of an ERET, this could potentially be used as part of a side-channel attack. This patch emits an SB sequence after each ERET so that speculation is held up on exception return. Signed-off-by: Will Deacon <will.deacon@arm.com>		2018-12-06 16:47:05 +00:00
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Makefile	kvm: arm64: Configure VTCR_EL2 per VM	2018-10-01 13:50:29 +01:00
debug-sr.c	KVM: arm64: Repurpose vcpu_arch.debug_flags for general-purpose flags	2018-05-25 12:28:13 +01:00
entry.S	arm64: entry: Place an SB sequence following an ERET instruction	2018-12-06 16:47:05 +00:00
fpsimd.S	arm64: KVM: Implement fpsimd save/restore	2015-12-14 11:30:41 +00:00
hyp-entry.S	arm64: entry: Place an SB sequence following an ERET instruction	2018-12-06 16:47:05 +00:00
switch.c	kvm: arm64: Add 52bit support for PAR to HPFAR conversoin	2018-10-01 13:50:32 +01:00
sysreg-sr.c	KVM updates for v4.20	2018-10-25 17:57:35 -07:00
tlb.c	kvm: arm64: Add helper for loading the stage2 setting for a VM	2018-10-01 13:08:41 +01:00
vgic-v2-cpuif-proxy.c	kvm/arm: use PSR_AA32 definitions	2018-07-05 17:24:15 +01:00