64 строки
1.9 KiB
Markdown
64 строки
1.9 KiB
Markdown
# Jacdac power
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JD device that delivers power to the bus needs to limit it.
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This document has notes on one way of implementing this.
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In both options:
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* add FET high-side switch on power delivery to the bus
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* probe current every 1ms, with slight randomization (eg. every 900-1100us)
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## Cheap option
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* add shunt resistor on the low side of power line (GND)
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* connect bus side of shunt to ADC via 3/5 voltage divider
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Assuming 12-bit ADC with reference voltage of 3.3V the table
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below gives precision of measurement per ADC step and voltage
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drop at 500mA.
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Shunt | Vdrop | Precision | Size
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-----:|------:|----------:|-----
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0.50Ω | 5.0% | 2.7mA | 0603
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0.36Ω | 3.6% | 3.7mA | 0402
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0.22Ω | 2.2% | 6.1mA | 0402
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0.20Ω | 2.0% | 6.7mA | 0402
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## Precise option
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* add INA199A1 current sensing amplifier (50V/V)
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* add shunt on either power or GND side
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Shunt | Vdrop | Precision | Max Curr | Size
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-----:|------:|----------:|---------:|------
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0.10Ω | 1.0% | 0.161mA | 660mA | 0603
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0.05Ω | 0.5% | 0.322mA | 1320mA | 0805
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0.02Ω | 0.2% | 0.806mA | 3300mA | 0805
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Additionally, can add additional switching FET and another shunt
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for precision measurements, when current is low.
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Voltage drops listed for 50mA.
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Shunt | Vdrop | Precision | Max Curr | Size
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-----:|------:|----------:|---------:|------
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1.00Ω | 1.0% | 0.016mA | 66mA | 0402
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0.50Ω | 0.5% | 0.032mA | 132mA | 0603
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## Low pass filters
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With 100Hz RC filter, if the current goes from max to 0,
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the voltage will drop by ~45% in 1ms. This represents
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a measure of error (the current we may miss when not sampling).
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OTOH, it takes 2ms for voltage to reach 70% when it goes from 0 to max,
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which is a measure of latency.
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With 50Hz, it drops by ~25% in 1ms and it takes 4ms to register
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70% of rise.
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With 25Hz, it drops by ~15% in 1ms and it takes 8ms to register
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70% of rise.
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50Hz is eg. 3.3kΩ and 1uF.
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Data from http://sim.okawa-denshi.jp/en/PWMtool.php
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