Граф коммитов

140 Коммитов

Автор SHA1 Сообщение Дата
Tianqi Chen 2548cedcb8 [OP/LANG] Support Extern Call, more regression tests (#69)
* [OP/LANG] Support Extern Call, more regression tests

* [TEST] Include pylintrc
2017-03-12 11:34:04 -07:00
Tianqi Chen b19e01bf27 [PASS] RemoveNoOp. (#68) 2017-03-11 20:12:42 -08:00
Tianqi Chen 88338826a4 [BUGFIX/TESTS] Bugfix of Tenso slicing. Union. (#66) 2017-03-07 11:37:11 -08:00
Tianqi Chen 3fb8579695 [REFACTOR] Add Types to IterVar, Isolate Operator (#62)
* [IterVar/REFACTOR] Add types to IterVar

* [ARITH/REFACTOR] Move IntSet to include

* [REFACTOR/OP] Move Op detail to seperate folder.

* fix test
2017-03-05 12:45:02 -08:00
Ziheng Jiang c8ebfbe355 [PASS]LoopPartition (#56)
* loop_partition draft

* divide loop variable into constant domain and variable domain & consider multiple partitions

* process doubt interval

* fix and refactor, add relax_map arg in BoundDeduce

* fix testcase and comment

* rebase to zero, convert to SSA

* change the logic of generating loop code & fix issues

* add a testcase for relax map in deducebound && fix issues

* clean code

* const auto&

* add test_multi_if
2017-03-03 21:09:39 -08:00
Tianqi Chen 24bca6af5d [TEST] Add dot (#61) 2017-03-02 22:21:19 -08:00
Tianqi Chen 2c512ca78d [LLVM] Vectorized load/store (#60) 2017-03-02 12:41:35 -08:00
Tianqi Chen 2111bbf338 Fix Travis on test (#59) 2017-02-28 18:16:56 -08:00
Tianqi Chen 7133448330 [VISITOR] New ExprFunctor, StmtFunctor Interface. Modular analysis (#58)
* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor

* retrigger

* [IRFunctor] Migrated CodegenC

* [IRFUNCTOR] Migrate CodeGenLLVM

* [IRFunctor] Migrate canonical

* [IRFunctor] Migrate vectorize

* [IRFunctor] migrate CodeGenStackVM
2017-02-28 16:16:09 -08:00
Tianqi Chen e43879405b [BUILD] Windows build pass on LLVM/CUDA/OPENCL (#57) 2017-02-27 14:30:46 -08:00
Tianqi Chen 3331020624 [BUILD] Add CMake for Windows build (#55) 2017-02-26 15:01:42 -08:00
Tianqi Chen f6c043eb79 [LLVM/RUNTIME] Support Parallel for on CPU (#54) 2017-02-25 23:20:39 -08:00
Tianqi Chen 2f462ccab5 [MODULE] Enable OpenCL and CUDA Modules (#53) 2017-02-25 20:08:02 -08:00
Tianqi Chen efae4be0bd [MODULE/REFACTOR] Introduce Module for AOT and runtime linking. (#51) 2017-02-24 10:32:11 -08:00
Tianqi Chen 8f240ee76d [CODEGEN/LLVM] Initial support for codegen LLVM. (#49)
* [LLVM] Initial support for codegen LLVM.

* Fix the naming issue of codegen
2017-02-22 10:47:54 -08:00
Ziheng Jiang 3555769efd [ARITH] Add CombineInterval<Div> in IntSet (#48)
* [FIX] add CombineInterval<Div>

* fix error message and add comment about rounding

* fix comment
2017-02-21 12:42:46 -08:00
Tianqi Chen c8ec41118d [SCAN/Refactor] Refactor scan interface, enable fix point analysis. (#47) 2017-02-20 13:09:23 -08:00
Ziheng Jiang 5198c10010 [ARITH] DeduceBound (#40)
* [PYTHON/API] Add compare and logic build-in op for Expr

* remove 'and', 'or'

* add deducer

* [WIP] bound_deducer.cc

* move IntervalSet and StrideSet into int_set_internal.h

* add multiple failure for VariablePathFinder, add EvalSign

* consider round in deduce, add success flag

* remove Visit_(Div)

* add comment, update HalideIR

* expose intset to python

* check the sign of every expr

* set return type as ExprSignType

* fine tune

* add min & max python api for interval set

* support for conditional expr

* refactor test

* add checker for BoundDeducer

* add python check test

* fix

* fix

* change range to interval; remove converter

* remove converter declaration

* remove int_set_internal.h
2017-02-17 10:56:48 -08:00
Tianqi Chen d114dfc96e [SCHEDULE] Mutate dataflow in schedule, refactor Stage (#44) 2017-02-16 19:08:50 -08:00
Tianqi Chen 820a85975f [LANG] Introduce Scan, Bugfix Canonical (#43) 2017-02-13 16:39:07 -08:00
Tianqi Chen f8f028295e [SCHEDULE] Refactor bound inference logic (#41) 2017-02-12 13:19:13 -08:00
Ziheng Jiang 5c07413cd4 [PASS] Change IRVisitor interfaces to function override (#42)
* [PASS] Change IRVisitor interfaces to function override

* [PASS] Change IRMutator interfaces to overloadable function
2017-02-11 21:55:57 -08:00
Tianqi Chen b8f0ec504c [LANG/PASS] InjectVirtualThread (#38) 2017-02-11 11:55:42 -08:00
Ziheng Jiang 526ff04c7e [PYTHON/API] Add compare and logic build-in op for Expr (#39)
* [PYTHON/API] Add compare and logic build-in op for Expr

* remove 'and', 'or'
2017-02-10 09:14:11 -08:00
Tianqi Chen 45597d0006 [LANG/PASS] Support Vectorize (#37) 2017-02-09 12:15:47 -08:00
Ziheng Jiang 6a62beb2b3 [FUSION] add 'void AutoFuseEwise(Schedule sch)' (#36)
* [FUSION] add Fusion(Schedule)

* [FUSION] rename to AutoFuseEwise, detect whether the stage has been scheduled

* [FUSION] change to visitor pattern

* [FUSION] rename filename

* [FUSION] fine-tune the interface

* [FUSION] typo

* move elem_wise to schedule

* rename test function
2017-02-08 22:33:52 -08:00
Tianqi Chen 08505e3484 [ADDON] Allow piggy back nvcc compiler and code (#35) 2017-02-07 08:12:54 -08:00
Tianqi Chen 8837798888 [PASS] Canonical form simplify (#34) 2017-02-06 16:26:15 -08:00
Ziheng Jiang 2bcf3f2c1f fix Stage.fuse (#33) 2017-02-05 12:04:24 -08:00
Tianqi Chen e42cc112bf [PASS] UnrollLoop, isolate arithmetic module. (#32) 2017-02-04 22:41:28 -08:00
Tianqi Chen d89917b670 [PASS] StorageFlatten and StorageSync, safe condition in schedul_ops, gemm example. (#31) 2017-02-04 15:46:25 -08:00
Tianqi Chen a2c8a29b21 [SCHEDULE] Improve bound inference, support reduce codegen. (#30) 2017-02-02 08:41:19 -08:00
Tianqi Chen d4af7ad6ab [TEST/PYTHON] Add unittest folder, add a build pipeline. Rename Buffer.ptr to Buffer.data to be consistent with Array. (#29) 2017-01-31 14:40:47 -08:00
Tianqi Chen 891630ed4d [CODEGEN/EXEC] CUDA, NVRTC pipeline complete (#27)
* [CODEGEN] CUDA/OPENCL pipeline complete

* Hide TVMType by str in frontend
2017-01-30 19:09:22 -08:00
Tianqi Chen ff06917c59 [API/Refactor] Unified PackedFunc for API and Generated Functions (#26) 2017-01-28 16:16:55 -08:00
Tianqi Chen 4242b9cff5 [API/JIT] Enable registerable global function, introduce StackVM intepreter (#25) 2017-01-24 23:47:07 -08:00
Tianqi Chen 01a7ce0cb6 [RUNTIME] Add Function, Unify TVMTypeCode and TVMArgTypeID (#24) 2017-01-23 21:41:04 -08:00
Tianqi Chen 4f1473f3a1 [CODEGEN] Add LoweredFunc, MakeAPI to build a C API function (#23)
* [CODEGEN] Add LoweredFunc, MakeAPI and SplitHostDevice

* update halideir
2017-01-22 17:45:31 -08:00
Tianqi Chen 3c1020dffb [CODEGEN] Add CodeGenC (#22) 2017-01-20 12:41:52 -08:00
Tianqi Chen 5b408d1da2 [IR] Move AttrStmt to HalideIR (#21) 2017-01-19 21:16:41 -08:00
Tianqi Chen 383494a51a [API] Move all RTTI related code to one place (#20)
* [API] Move all RTTI related code to one place

* add back rtti comment
2017-01-19 07:42:33 -08:00
Tianqi Chen 4d4e19ce0a [TESTCASE] Add a mock test workflow of CUDA codegen (#19) 2017-01-18 15:13:52 -08:00
Haichen Shen 110c9bec74 [PASS] Assign unique names to variables in ConvertSSA pass (#18)
* [PASS] Assign unique names to variables in ConvertSSA pass

* revert change to ConverSSA pass
2017-01-18 14:48:16 -08:00
Tianqi Chen 9e1a5ec449 [RUNTIME] Enable OpenCL (#17) 2017-01-17 21:13:16 -08:00
Tianqi Chen e9ff9a8989 [RUNTIME] Finish GPU runtime and python interface (#16)
* [RUNTIME] Finish GPU runtime and python interface

* fix travis test

* fix build
2017-01-17 14:07:38 -08:00
Haichen Shen f2f1526daa [PASS] Export simplify and equal to python (#14)
* [PASS] Export simplify and equal to python

* fix naming convention
2017-01-16 14:53:47 -08:00
Tianqi Chen 7e025234fe [RUNTIME] Add interface header of runtime (#15)
* [RUNTIME] Add interface header of runtime

* fix mac build
2017-01-16 14:53:26 -08:00
Tianqi Chen 7f82912bfb [PASS] Basic storage flatten (#13) 2017-01-15 21:40:21 -08:00
Tianqi Chen 0992873af2 [LANG] Include buffer semnatics, introduce pylint (#11)
* [LANG] Include buffer semnatics, introduce pylint

* Refactor inline add support for buffer indexing

* fix doc
2017-01-13 15:40:49 -08:00
Haichen Shen 69a80ccee7 add simplify test (#12) 2017-01-13 15:09:37 -08:00