2006-05-24 04:18:44 +04:00
|
|
|
#
|
|
|
|
|
# DMA engine configuration
|
|
|
|
|
#
|
|
|
|
|
|
2007-10-16 12:27:42 +04:00
|
|
|
menuconfig DMADEVICES
|
2007-11-29 03:21:43 +03:00
|
|
|
bool "DMA Engine support"
|
2009-06-04 01:22:28 +04:00
|
|
|
depends on HAS_DMA
|
2007-10-16 12:27:42 +04:00
|
|
|
help
|
2007-11-29 03:21:43 +03:00
|
|
|
DMA engines can do asynchronous data transfers without
|
|
|
|
|
involving the host CPU. Currently, this framework can be
|
|
|
|
|
used to offload memory copies in the network stack and
|
2008-06-27 12:21:11 +04:00
|
|
|
RAID operations in the MD driver. This menu only presents
|
|
|
|
|
DMA Device drivers supported by the configured arch, it may
|
|
|
|
|
be empty in some cases.
|
2007-10-16 12:27:42 +04:00
|
|
|
|
2010-02-10 00:34:54 +03:00
|
|
|
config DMADEVICES_DEBUG
|
|
|
|
|
bool "DMA Engine debugging"
|
|
|
|
|
depends on DMADEVICES != n
|
|
|
|
|
help
|
|
|
|
|
This is an option for use by developers; most people should
|
|
|
|
|
say N here. This enables DMA engine core and driver debugging.
|
|
|
|
|
|
|
|
|
|
config DMADEVICES_VDEBUG
|
|
|
|
|
bool "DMA Engine verbose debugging"
|
|
|
|
|
depends on DMADEVICES_DEBUG != n
|
|
|
|
|
help
|
|
|
|
|
This is an option for use by developers; most people should
|
|
|
|
|
say N here. This enables deeper (more verbose) debugging of
|
|
|
|
|
the DMA engine core and drivers.
|
|
|
|
|
|
|
|
|
|
|
2007-10-16 12:27:42 +04:00
|
|
|
if DMADEVICES
|
|
|
|
|
|
|
|
|
|
comment "DMA Devices"
|
|
|
|
|
|
2010-07-21 11:58:10 +04:00
|
|
|
config INTEL_MID_DMAC
|
|
|
|
|
tristate "Intel MID DMA support for Peripheral DMA controllers"
|
|
|
|
|
depends on PCI && X86
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) MID DMA engine present
|
|
|
|
|
in Intel MID chipsets.
|
|
|
|
|
|
|
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-10-08 03:44:50 +04:00
|
|
|
config ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2009-09-09 04:42:51 +04:00
|
|
|
bool
|
|
|
|
|
|
2010-09-28 17:57:37 +04:00
|
|
|
config AMBA_PL08X
|
|
|
|
|
bool "ARM PrimeCell PL080 or PL081 support"
|
|
|
|
|
depends on ARM_AMBA && EXPERIMENTAL
|
|
|
|
|
select DMA_ENGINE
|
2012-05-26 17:09:53 +04:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2010-09-28 17:57:37 +04:00
|
|
|
help
|
|
|
|
|
Platform has a PL08x DMAC device
|
|
|
|
|
which can provide DMA engine support
|
|
|
|
|
|
2007-10-16 12:27:42 +04:00
|
|
|
config INTEL_IOATDMA
|
|
|
|
|
tristate "Intel I/OAT DMA support"
|
|
|
|
|
depends on PCI && X86
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DCA
|
2009-11-20 03:10:37 +03:00
|
|
|
select ASYNC_TX_DISABLE_PQ_VAL_DMA
|
|
|
|
|
select ASYNC_TX_DISABLE_XOR_VAL_DMA
|
2007-10-16 12:27:42 +04:00
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) I/OAT DMA engine present
|
|
|
|
|
in recent Intel Xeon chipsets.
|
|
|
|
|
|
|
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config INTEL_IOP_ADMA
|
|
|
|
|
tristate "Intel IOP ADMA support"
|
|
|
|
|
depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
|
|
|
|
|
select DMA_ENGINE
|
2010-10-08 03:44:50 +04:00
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2007-10-16 12:27:42 +04:00
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) IOP Series RAID engines.
|
2006-05-24 04:18:44 +04:00
|
|
|
|
2008-07-08 22:59:42 +04:00
|
|
|
config DW_DMAC
|
|
|
|
|
tristate "Synopsys DesignWare AHB DMA support"
|
2011-03-03 13:17:14 +03:00
|
|
|
depends on HAVE_CLK
|
2008-07-08 22:59:42 +04:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
default y if CPU_AT32AP7000
|
|
|
|
|
help
|
|
|
|
|
Support the Synopsys DesignWare AHB DMA controller. This
|
|
|
|
|
can be integrated in chips such as the Atmel AT32ap7000.
|
|
|
|
|
|
2012-10-26 00:38:05 +04:00
|
|
|
config DW_DMAC_BIG_ENDIAN_IO
|
|
|
|
|
bool "Use big endian I/O register access"
|
|
|
|
|
default y if AVR32
|
|
|
|
|
depends on DW_DMAC
|
|
|
|
|
help
|
|
|
|
|
Say yes here to use big endian I/O access when reading and writing
|
|
|
|
|
to the DMA controller registers. This is needed on some platforms,
|
|
|
|
|
like the Atmel AVR32 architecture.
|
|
|
|
|
|
|
|
|
|
If unsure, use the default setting.
|
|
|
|
|
|
2009-07-03 21:24:33 +04:00
|
|
|
config AT_HDMAC
|
|
|
|
|
tristate "Atmel AHB DMA support"
|
2012-03-15 14:31:58 +04:00
|
|
|
depends on ARCH_AT91
|
2009-07-03 21:24:33 +04:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2012-03-15 14:31:58 +04:00
|
|
|
Support the Atmel AHB DMA controller.
|
2009-07-03 21:24:33 +04:00
|
|
|
|
2008-03-01 17:42:48 +03:00
|
|
|
config FSL_DMA
|
2008-09-27 04:00:11 +04:00
|
|
|
tristate "Freescale Elo and Elo Plus DMA support"
|
|
|
|
|
depends on FSL_SOC
|
2008-03-01 17:42:48 +03:00
|
|
|
select DMA_ENGINE
|
2010-10-08 03:44:50 +04:00
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2008-03-01 17:42:48 +03:00
|
|
|
---help---
|
2008-09-27 04:00:11 +04:00
|
|
|
Enable support for the Freescale Elo and Elo Plus DMA controllers.
|
|
|
|
|
The Elo is the DMA controller on some 82xx and 83xx parts, and the
|
|
|
|
|
Elo Plus is the DMA controller on 85xx and 86xx parts.
|
2008-03-01 17:42:48 +03:00
|
|
|
|
2010-02-05 06:42:52 +03:00
|
|
|
config MPC512X_DMA
|
|
|
|
|
tristate "Freescale MPC512x built-in DMA engine support"
|
2010-10-27 03:52:57 +04:00
|
|
|
depends on PPC_MPC512x || PPC_MPC831x
|
2010-02-05 06:42:52 +03:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
---help---
|
|
|
|
|
Enable support for the Freescale MPC512x built-in DMA engine.
|
|
|
|
|
|
2008-07-08 22:58:36 +04:00
|
|
|
config MV_XOR
|
|
|
|
|
bool "Marvell XOR engine support"
|
|
|
|
|
depends on PLAT_ORION
|
|
|
|
|
select DMA_ENGINE
|
2010-10-08 03:44:50 +04:00
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2008-07-08 22:58:36 +04:00
|
|
|
---help---
|
|
|
|
|
Enable support for the Marvell XOR engine.
|
|
|
|
|
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
|
|
|
config MX3_IPU
|
|
|
|
|
bool "MX3x Image Processing Unit support"
|
2011-08-24 10:41:09 +04:00
|
|
|
depends on ARCH_MXC
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
If you plan to use the Image Processing unit in the i.MX3x, say
|
|
|
|
|
Y here. If unsure, select Y.
|
|
|
|
|
|
|
|
|
|
config MX3_IPU_IRQS
|
|
|
|
|
int "Number of dynamically mapped interrupts for IPU"
|
|
|
|
|
depends on MX3_IPU
|
|
|
|
|
range 2 137
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
|
|
|
|
|
To avoid bloating the irq_desc[] array we allocate a sufficient
|
|
|
|
|
number of IRQ slots and map them dynamically to specific sources.
|
|
|
|
|
|
2009-04-22 19:40:30 +04:00
|
|
|
config TXX9_DMAC
|
|
|
|
|
tristate "Toshiba TXx9 SoC DMA support"
|
|
|
|
|
depends on MACH_TX49XX || MACH_TX39XX
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the TXx9 SoC internal DMA controller. This can be
|
|
|
|
|
integrated in chips such as the Toshiba TX4927/38/39.
|
|
|
|
|
|
2012-06-06 09:25:27 +04:00
|
|
|
config TEGRA20_APB_DMA
|
|
|
|
|
bool "NVIDIA Tegra20 APB DMA support"
|
|
|
|
|
depends on ARCH_TEGRA
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra20 APB DMA controller driver. The
|
|
|
|
|
DMA controller is having multiple DMA channel which can be
|
|
|
|
|
configured for different peripherals like audio, UART, SPI,
|
|
|
|
|
I2C etc which is in APB bus.
|
|
|
|
|
This DMA controller transfers data from memory to peripheral fifo
|
|
|
|
|
or vice versa. It does not support memory to memory data transfer.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2009-09-07 07:26:23 +04:00
|
|
|
config SH_DMAE
|
|
|
|
|
tristate "Renesas SuperH DMAC support"
|
2010-03-19 07:47:19 +03:00
|
|
|
depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
|
2009-09-07 07:26:23 +04:00
|
|
|
depends on !SH_DMA_API
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Renesas SuperH DMA controllers.
|
|
|
|
|
|
2009-11-19 21:49:17 +03:00
|
|
|
config COH901318
|
|
|
|
|
bool "ST-Ericsson COH901318 DMA support"
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
depends on ARCH_U300
|
|
|
|
|
help
|
|
|
|
|
Enable support for ST-Ericsson COH 901 318 DMA.
|
|
|
|
|
|
2010-03-30 17:33:42 +04:00
|
|
|
config STE_DMA40
|
|
|
|
|
bool "ST-Ericsson DMA40 support"
|
|
|
|
|
depends on ARCH_U8500
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support for ST-Ericsson DMA40 controller
|
|
|
|
|
|
2009-12-12 07:24:44 +03:00
|
|
|
config AMCC_PPC440SPE_ADMA
|
|
|
|
|
tristate "AMCC PPC440SPe ADMA support"
|
|
|
|
|
depends on 440SPe || 440SP
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
|
2010-10-08 03:44:50 +04:00
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2009-12-12 07:24:44 +03:00
|
|
|
help
|
|
|
|
|
Enable support for the AMCC PPC440SPe RAID engines.
|
|
|
|
|
|
2010-03-25 21:44:21 +03:00
|
|
|
config TIMB_DMA
|
|
|
|
|
tristate "Timberdale FPGA DMA support"
|
|
|
|
|
depends on MFD_TIMBERDALE || HAS_IOMEM
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Timberdale FPGA DMA engine.
|
|
|
|
|
|
2011-10-28 06:22:39 +04:00
|
|
|
config SIRF_DMA
|
|
|
|
|
tristate "CSR SiRFprimaII DMA support"
|
|
|
|
|
depends on ARCH_PRIMA2
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the CSR SiRFprimaII DMA engine.
|
|
|
|
|
|
2012-08-23 05:09:34 +04:00
|
|
|
config TI_EDMA
|
|
|
|
|
tristate "TI EDMA support"
|
|
|
|
|
depends on ARCH_DAVINCI
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable support for the TI EDMA controller. This DMA
|
|
|
|
|
engine is found on TI DaVinci and AM33xx parts.
|
|
|
|
|
|
2009-12-12 07:24:44 +03:00
|
|
|
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
|
|
|
|
|
bool
|
|
|
|
|
|
2010-05-24 07:28:19 +04:00
|
|
|
config PL330_DMA
|
|
|
|
|
tristate "DMA API Driver for PL330"
|
|
|
|
|
select DMA_ENGINE
|
2011-09-02 04:44:30 +04:00
|
|
|
depends on ARM_AMBA
|
2010-05-24 07:28:19 +04:00
|
|
|
help
|
|
|
|
|
Select if your platform has one or more PL330 DMACs.
|
|
|
|
|
You need to provide platform specific settings via
|
|
|
|
|
platform_data for a dma-pl330 device.
|
|
|
|
|
|
2010-07-30 12:23:03 +04:00
|
|
|
config PCH_DMA
|
2011-11-17 11:14:23 +04:00
|
|
|
tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
|
2010-07-30 12:23:03 +04:00
|
|
|
depends on PCI && X86
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2011-01-05 11:43:52 +03:00
|
|
|
Enable support for Intel EG20T PCH DMA engine.
|
|
|
|
|
|
2011-11-17 11:14:22 +04:00
|
|
|
This driver also can be used for LAPIS Semiconductor IOH(Input/
|
2011-11-17 11:14:23 +04:00
|
|
|
Output Hub), ML7213, ML7223 and ML7831.
|
|
|
|
|
ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
|
|
|
|
|
for MP(Media Phone) use and ML7831 IOH is for general purpose use.
|
|
|
|
|
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
|
|
|
|
|
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
|
2010-07-30 12:23:03 +04:00
|
|
|
|
2010-09-30 17:56:34 +04:00
|
|
|
config IMX_SDMA
|
|
|
|
|
tristate "i.MX SDMA support"
|
2011-08-24 10:41:09 +04:00
|
|
|
depends on ARCH_MXC
|
2010-09-30 17:56:34 +04:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the i.MX SDMA engine. This engine is integrated into
|
2011-08-24 10:41:09 +04:00
|
|
|
Freescale i.MX25/31/35/51/53 chips.
|
2010-09-30 17:56:34 +04:00
|
|
|
|
2010-10-06 12:25:55 +04:00
|
|
|
config IMX_DMA
|
|
|
|
|
tristate "i.MX DMA support"
|
2012-03-27 12:23:00 +04:00
|
|
|
depends on ARCH_MXC
|
2010-10-06 12:25:55 +04:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the i.MX DMA engine. This engine is integrated into
|
|
|
|
|
Freescale i.MX1/21/27 chips.
|
|
|
|
|
|
2011-02-26 19:47:42 +03:00
|
|
|
config MXS_DMA
|
|
|
|
|
bool "MXS DMA support"
|
2012-06-07 05:22:59 +04:00
|
|
|
depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
|
2012-05-04 16:12:15 +04:00
|
|
|
select STMP_DEVICE
|
2011-02-26 19:47:42 +03:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the MXS DMA engine. This engine including APBH-DMA
|
|
|
|
|
and APBX-DMA is integrated into Freescale i.MX23/28 chips.
|
|
|
|
|
|
2011-05-29 14:10:02 +04:00
|
|
|
config EP93XX_DMA
|
|
|
|
|
bool "Cirrus Logic EP93xx DMA support"
|
|
|
|
|
depends on ARCH_EP93XX
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
|
|
|
|
|
|
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 01:44:07 +04:00
|
|
|
config DMA_SA11X0
|
|
|
|
|
tristate "SA-11x0 DMA support"
|
|
|
|
|
depends on ARCH_SA1100
|
|
|
|
|
select DMA_ENGINE
|
2012-04-13 15:07:23 +04:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 01:44:07 +04:00
|
|
|
help
|
|
|
|
|
Support the DMA engine found on Intel StrongARM SA-1100 and
|
|
|
|
|
SA-1110 SoCs. This DMA engine can only be used with on-chip
|
|
|
|
|
devices.
|
|
|
|
|
|
2012-06-15 07:04:08 +04:00
|
|
|
config MMP_TDMA
|
|
|
|
|
bool "MMP Two-Channel DMA support"
|
2012-06-22 08:59:53 +04:00
|
|
|
depends on ARCH_MMP
|
2012-06-15 07:04:08 +04:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the MMP Two-Channel DMA engine.
|
|
|
|
|
This engine used for MMP Audio DMA and pxa910 SQU.
|
|
|
|
|
|
|
|
|
|
Say Y here if you enabled MMP ADMA, otherwise say N.
|
|
|
|
|
|
2012-04-13 15:10:24 +04:00
|
|
|
config DMA_OMAP
|
|
|
|
|
tristate "OMAP DMA support"
|
|
|
|
|
depends on ARCH_OMAP
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
|
dmaengine: mmp-pdma support
1. virtual channel vs. physical channel
Virtual channel is managed by dmaengine
Physical channel handling resource, such as irq
Physical channel is alloced dynamically as descending priority,
freed immediately when irq done.
The availble highest priority physically channel will alwayes be alloced
Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel
2. list: running list & pending list
submit: desc list -> pending list
issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
irq: free running list (IDLE)
check pendlist -> pending list -> running list; free pending list (RUN)
3. irq:
Each list generate one irq, calling callback
One list may contain several desc chain, in such case, make sure only the last desc list generate irq.
4. async
Submit will add desc chain to pending list, which can be multi-called
If multi desc chain is submitted, only the last desc would generate irq -> call back
If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
If RUN, irq will start pending list
5. test
5.1 pxa3xx_nand on pxa910
5.2 insmod dmatest.ko (threads_per_chan=y)
By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-09-03 07:03:45 +04:00
|
|
|
config MMP_PDMA
|
|
|
|
|
bool "MMP PDMA support"
|
|
|
|
|
depends on (ARCH_MMP || ARCH_PXA)
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support the MMP PDMA engine for PXA and MMP platfrom.
|
|
|
|
|
|
2006-05-24 04:18:44 +04:00
|
|
|
config DMA_ENGINE
|
2007-10-16 12:27:42 +04:00
|
|
|
bool
|
2006-05-24 04:18:44 +04:00
|
|
|
|
2012-04-13 15:07:23 +04:00
|
|
|
config DMA_VIRTUAL_CHANNELS
|
|
|
|
|
tristate
|
|
|
|
|
|
2006-06-18 08:24:58 +04:00
|
|
|
comment "DMA Clients"
|
2007-10-16 12:27:42 +04:00
|
|
|
depends on DMA_ENGINE
|
2006-06-18 08:24:58 +04:00
|
|
|
|
|
|
|
|
config NET_DMA
|
|
|
|
|
bool "Network: TCP receive copy offload"
|
|
|
|
|
depends on DMA_ENGINE && NET
|
2008-06-27 12:21:11 +04:00
|
|
|
default (INTEL_IOATDMA || FSL_DMA)
|
2007-10-16 12:27:42 +04:00
|
|
|
help
|
2006-06-18 08:24:58 +04:00
|
|
|
This enables the use of DMA engines in the network stack to
|
|
|
|
|
offload receive copy-to-user operations, freeing CPU cycles.
|
2008-06-27 12:21:11 +04:00
|
|
|
|
|
|
|
|
Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
|
|
|
|
|
say N.
|
2006-06-18 08:24:58 +04:00
|
|
|
|
2009-03-25 19:13:25 +03:00
|
|
|
config ASYNC_TX_DMA
|
|
|
|
|
bool "Async_tx: Offload support for the async_tx api"
|
2009-09-09 02:06:10 +04:00
|
|
|
depends on DMA_ENGINE
|
2009-03-25 19:13:25 +03:00
|
|
|
help
|
|
|
|
|
This allows the async_tx api to take advantage of offload engines for
|
|
|
|
|
memcpy, memset, xor, and raid6 p+q operations. If your platform has
|
|
|
|
|
a dma engine that can perform raid operations and you have enabled
|
|
|
|
|
MD_RAID456 say Y.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2008-07-08 22:58:45 +04:00
|
|
|
config DMATEST
|
|
|
|
|
tristate "DMA Test client"
|
|
|
|
|
depends on DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Simple DMA test client. Say N unless you're debugging a
|
|
|
|
|
DMA Device driver.
|
|
|
|
|
|
2007-10-16 12:27:42 +04:00
|
|
|
endif
|
