Merge branch 'remotes/lorenzo/pci/mediatek'
- Split DT bindings for PCIe controllers with independent MSI domains into separate nodes for MT2712/MT7622 (Chuanjia Liu) - Locate shared registers from "mediatek,generic-pciecfg" property (Chuanjia Liu) - Get IRQ from "pcie_irq" if "interrupt-names" property is present to fix an MSI issue (Chuanjia Liu) - Get PCI domain from "linux,pci-domain" property if present (Chuanjia Liu) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Use PCI domain to handle ports detection PCI: mediatek: Add new method to get irq number PCI: mediatek: Add new method to get shared pcie-cfg base address dt-bindings: PCI: mediatek: Update the Device tree bindings
This commit is contained in:
Bjorn Helgaas
Коммит
c501cf9cbe
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@ -0,0 +1,39 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIECFG controller
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maintainers:
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- Chuanjia Liu <chuanjia.liu@mediatek.com>
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- Jianjun Wang <jianjun.wang@mediatek.com>
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description: |
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The MediaTek PCIECFG controller controls some feature about
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LTSSM, ASPM and so on.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,generic-pciecfg
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- const: syscon
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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pciecfg: pciecfg@1a140000 {
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compatible = "mediatek,generic-pciecfg", "syscon";
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reg = <0x1a140000 0x1000>;
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};
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...
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@ -8,7 +8,7 @@ Required properties:
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"mediatek,mt7623-pcie"
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"mediatek,mt7629-pcie"
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- device_type: Must be "pci"
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- reg: Base addresses and lengths of the PCIe subsys and root ports.
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- reg: Base addresses and lengths of the root ports.
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- reg-names: Names of the above areas to use during resource lookup.
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- #address-cells: Address representation for root ports (must be 3)
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- #size-cells: Size representation for root ports (must be 2)
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@ -47,9 +47,12 @@ Required properties for MT7623/MT2701:
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- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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number of root ports.
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Required properties for MT2712/MT7622:
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Required properties for MT2712/MT7622/MT7629:
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-interrupts: A list of interrupt outputs of the controller, must have one
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entry for each PCIe port
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- interrupt-names: Must include the following entries:
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- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
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- linux,pci-domain: PCI domain ID. Should be unique for each host controller
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In addition, the device tree node must have sub-nodes describing each
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PCIe port interface, having the following mandatory properties:
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@ -143,130 +146,143 @@ Examples for MT7623:
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Examples for MT2712:
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pcie: pcie@11700000 {
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pcie1: pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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reg = <0 0x11700000 0 0x1000>,
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<0 0x112ff000 0 0x1000>;
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reg-names = "port0", "port1";
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reg = <0 0x112ff000 0 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE0>,
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE1>;
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clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0", "pcie-phy1";
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clock-names = "sys_ck1", "ahb_ck1";
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phys = <&u3port1 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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status = "disabled";
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pcie0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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pcie1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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pcie0: pcie@11700000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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reg = <0 0x11700000 0 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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<&pericfg CLK_PERI_PCIE0>;
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clock-names = "sys_ck0", "ahb_ck0";
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phys = <&u3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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Examples for MT7622:
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pcie: pcie@1a140000 {
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pcie0: pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0 0x1a140000 0 0x1000>,
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<0 0x1a143000 0 0x1000>,
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<0 0x1a145000 0 0x1000>;
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reg-names = "subsys", "port0", "port1";
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reg = <0 0x1a143000 0 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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<&pciesys CLK_PCIE_P1_MAC_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P1_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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<&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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<&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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<&pciesys CLK_PCIE_P1_OBFF_EN>,
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<&pciesys CLK_PCIE_P0_PIPE_EN>,
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<&pciesys CLK_PCIE_P1_PIPE_EN>;
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clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0", "pcie-phy1";
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<&pciesys CLK_PCIE_P0_PIPE_EN>;
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clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
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"axi_ck0", "obff_ck0", "pipe_ck0";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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status = "disabled";
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pcie0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1a145000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0 0x1a145000 0 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
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/* designer has connect RC1 with p0_ahb clock */
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P1_OBFF_EN>,
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<&pciesys CLK_PCIE_P1_PIPE_EN>;
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clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
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"axi_ck1", "obff_ck1", "pipe_ck1";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
|
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
|
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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|
|
|
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|
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@ -14,6 +14,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
|
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#include <linux/kernel.h>
|
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#include <linux/mfd/syscon.h>
|
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#include <linux/msi.h>
|
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#include <linux/module.h>
|
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#include <linux/of_address.h>
|
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|
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@ -23,6 +24,7 @@
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#include <linux/phy/phy.h>
|
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#include <linux/platform_device.h>
|
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#include <linux/pm_runtime.h>
|
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#include <linux/regmap.h>
|
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#include <linux/reset.h>
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|
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#include "../pci.h"
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|
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@ -207,6 +209,7 @@ struct mtk_pcie_port {
|
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* struct mtk_pcie - PCIe host information
|
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* @dev: pointer to PCIe device
|
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* @base: IO mapped register base
|
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* @cfg: IO mapped register map for PCIe config
|
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* @free_ck: free-run reference clock
|
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* @mem: non-prefetchable memory resource
|
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* @ports: pointer to PCIe port information
|
||||
|
|
@ -215,6 +218,7 @@ struct mtk_pcie_port {
|
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struct mtk_pcie {
|
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struct device *dev;
|
||||
void __iomem *base;
|
||||
struct regmap *cfg;
|
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struct clk *free_ck;
|
||||
|
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struct list_head ports;
|
||||
|
|
@ -646,7 +650,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
|
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return err;
|
||||
}
|
||||
|
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port->irq = platform_get_irq(pdev, port->slot);
|
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if (of_find_property(dev->of_node, "interrupt-names", NULL))
|
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port->irq = platform_get_irq_byname(pdev, "pcie_irq");
|
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else
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port->irq = platform_get_irq(pdev, port->slot);
|
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|
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if (port->irq < 0)
|
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return port->irq;
|
||||
|
||||
|
|
@ -678,6 +686,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
|
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val |= PCIE_CSR_LTSSM_EN(port->slot) |
|
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PCIE_CSR_ASPM_L1_EN(port->slot);
|
||||
writel(val, pcie->base + PCIE_SYS_CFG_V2);
|
||||
} else if (pcie->cfg) {
|
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val = PCIE_CSR_LTSSM_EN(port->slot) |
|
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PCIE_CSR_ASPM_L1_EN(port->slot);
|
||||
regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
|
||||
}
|
||||
|
||||
/* Assert all reset signals */
|
||||
|
|
@ -981,6 +993,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
|
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struct device *dev = pcie->dev;
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct resource *regs;
|
||||
struct device_node *cfg_node;
|
||||
int err;
|
||||
|
||||
/* get shared registers, which are optional */
|
||||
|
|
@ -991,6 +1004,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
|
|||
return PTR_ERR(pcie->base);
|
||||
}
|
||||
|
||||
cfg_node = of_find_compatible_node(NULL, NULL,
|
||||
"mediatek,generic-pciecfg");
|
||||
if (cfg_node) {
|
||||
pcie->cfg = syscon_node_to_regmap(cfg_node);
|
||||
if (IS_ERR(pcie->cfg))
|
||||
return PTR_ERR(pcie->cfg);
|
||||
}
|
||||
|
||||
pcie->free_ck = devm_clk_get(dev, "free_ck");
|
||||
if (IS_ERR(pcie->free_ck)) {
|
||||
if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
|
||||
|
|
@ -1023,22 +1044,27 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
|
|||
struct device *dev = pcie->dev;
|
||||
struct device_node *node = dev->of_node, *child;
|
||||
struct mtk_pcie_port *port, *tmp;
|
||||
int err;
|
||||
int err, slot;
|
||||
|
||||
for_each_available_child_of_node(node, child) {
|
||||
int slot;
|
||||
slot = of_get_pci_domain_nr(dev->of_node);
|
||||
if (slot < 0) {
|
||||
for_each_available_child_of_node(node, child) {
|
||||
err = of_pci_get_devfn(child);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to get devfn: %d\n", err);
|
||||
goto error_put_node;
|
||||
}
|
||||
|
||||
err = of_pci_get_devfn(child);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to parse devfn: %d\n", err);
|
||||
goto error_put_node;
|
||||
slot = PCI_SLOT(err);
|
||||
|
||||
err = mtk_pcie_parse_port(pcie, child, slot);
|
||||
if (err)
|
||||
goto error_put_node;
|
||||
}
|
||||
|
||||
slot = PCI_SLOT(err);
|
||||
|
||||
err = mtk_pcie_parse_port(pcie, child, slot);
|
||||
} else {
|
||||
err = mtk_pcie_parse_port(pcie, node, slot);
|
||||
if (err)
|
||||
goto error_put_node;
|
||||
return err;
|
||||
}
|
||||
|
||||
err = mtk_pcie_subsys_powerup(pcie);
|
||||
|
|
|
|||
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Ссылка в новой задаче