Граф коммитов

199 Коммитов

Автор SHA1 Сообщение Дата
Linus Torvalds 0c85556318 ARM: platform support for Apple M1
The Apple M1 is the processor used it all current generation Apple
 Macintosh computers. Support for this platform so far is rudimentary,
 but it boots and can use framebuffer and serial console over a special
 USB cable.
 
 Support for several essential on-chip devices (USB, PCIe, IOMMU, NVMe)
 is work in progress but was not ready in time.
 
 A very detailed description of what works is in the merge commit
 and on the AsahiLinux wiki.
 
 Link: https://lore.kernel.org/linux-arm-kernel/bdb18e9f-fcd7-1e31-2224-19c0e5090706@marcan.st/
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmCC2eIACgkQmmx57+YA
 GNkAGg/+NY3MKphm1fhJB7X66fZwviBUt6OTiZnbAHxIX7WChgM05KvxLUFXXpDI
 0E/YZU18no1YxioyLMEH+BJoZjO8fT1lu/H40KVepbx1uHI8k0pnf7qFOdWy48se
 X87dunxR0Mo4iR94sDKUAEaeXuFA0xxoQLLipCn00/rN5xx6K3OL4g1Gh42bS4L8
 f8ThQ/MuU7KksJjMy8YO99g2REmzGkE40ptAPc/InUln7lCJPTTmMO9a14uP9T1i
 B5uQTKOihlln1RiFCmxgKl+YKeJIxNtk9FpyEJNxTrPzcUX6SDwro9A7OZdK1wVM
 v/i4t2acI16670iqzf/HZg+0zGuV8xc5Axn0+PBNdA/ZdDPnmB8ej0uJhty4fI2j
 nTDBS32OtdkBk+aRZthFGTt6fYEcy5hdkMQJinBKObLZbZBBPwF6P1WSGXS3AHVC
 EKZf+Vh5MVyl3t5BJgDsyCmLC8p7uJYt2NzMLcCWJbKppR7dxXSByAO8JtuExEP3
 Y0RjChsR87y9yzMRcy/MqLy57YwpEEmTjE2wH8UKmNzYBRFZcV1uaWX1oRhWfPJw
 NGXHzpNhlC0gVk6OvIA9t6X9fQ590FWdJmVlIPIjiWJ/LHP/idmyZu+7F1H6v3/k
 Ah1EVqzwsksbS8iWZlhYJB5S+tSVvtW5ZUgUQtz1VSQrT1wwKJ4=
 =pBZy
 -----END PGP SIGNATURE-----

Merge tag 'arm-apple-m1-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Apple M1 platform support from Arnd Bergmann:
 "The Apple M1 is the processor used it all current generation Apple
  Macintosh computers. Support for this platform so far is rudimentary,
  but it boots and can use framebuffer and serial console over a special
  USB cable.

  Support for several essential on-chip devices (USB, PCIe, IOMMU, NVMe)
  is work in progress but was not ready in time.

  A very detailed description of what works is in the commit message of
  commit 1bb2fd3880 ("Merge tag 'm1-soc-bringup-v5' [..]") and on the
  AsahiLinux wiki"

Link: https://lore.kernel.org/linux-arm-kernel/bdb18e9f-fcd7-1e31-2224-19c0e5090706@marcan.st/

* tag 'arm-apple-m1-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  asm-generic/io.h: Unbork ioremap_np() declaration
  arm64: apple: Add initial Apple Mac mini (M1, 2020) devicetree
  dt-bindings: display: Add apple,simple-framebuffer
  arm64: Kconfig: Introduce CONFIG_ARCH_APPLE
  irqchip/apple-aic: Add support for the Apple Interrupt Controller
  dt-bindings: interrupt-controller: Add DT bindings for apple-aic
  arm64: Move ICH_ sysreg bits from arm-gic-v3.h to sysreg.h
  of/address: Add infrastructure to declare MMIO as non-posted
  asm-generic/io.h: implement pci_remap_cfgspace using ioremap_np
  arm64: Implement ioremap_np() to map MMIO as nGnRnE
  docs: driver-api: device-io: Document ioremap() variants & access funcs
  docs: driver-api: device-io: Document I/O access functions
  asm-generic/io.h:  Add a non-posted variant of ioremap()
  arm64: arch_timer: Implement support for interrupt-names
  dt-bindings: timer: arm,arch_timer: Add interrupt-names support
  arm64: cputype: Add CPU implementor & types for the Apple M1 cores
  dt-bindings: arm: cpus: Add apple,firestorm & icestorm compatibles
  dt-bindings: arm: apple: Add bindings for Apple ARM platforms
  dt-bindings: vendor-prefixes: Add apple prefix
2021-04-26 12:30:36 -07:00
Thomas Bogendoerfer 529ea36818 irqchip: Add support for IDT 79rc3243x interrupt controller
IDT 79rc3243x SoCs have rather simple interrupt controllers connected
to the MIPS CPU interrupt lines. Each of them has room for up to
32 interrupts.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210422145330.73452-1-tsbogend@alpha.franken.de
2021-04-22 16:03:18 +01:00
Hector Martin 76cde26394 irqchip/apple-aic: Add support for the Apple Interrupt Controller
This is the root interrupt controller used on Apple ARM SoCs such as the
M1. This irqchip driver performs multiple functions:

* Handles both IRQs and FIQs

* Drives the AIC peripheral itself (which handles IRQs)

* Dispatches FIQs to downstream hard-wired clients (currently the ARM
  timer).

* Implements a virtual IPI multiplexer to funnel multiple Linux IPIs
  into a single hardware IPI

Reviewed-by: Marc Zyngier <maz@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08 20:18:41 +09:00
Jonathan Neuschäfer fead4dd496 irqchip: Add driver for WPCM450 interrupt controller
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
SoCs.

The list of registers if based on the AMI vendor kernel and the
Nuvoton W90N745 datasheet.

Although the hardware supports other interrupt modes, the driver only
supports high-level interrupts at the moment, because other modes could
not be tested so far.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210406120921.2484986-7-j.neuschaefer@gmx.net
2021-04-07 13:26:00 +01:00
Bert Vermeulen 9f3a0f34b8 irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller
This is a standard IRQ driver with only status and mask registers.

The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.

Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com
2021-02-04 10:36:15 +00:00
Samuel Holland 4e34614636 irqchip/sun6i-r: Use a stacked irqchip driver
The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
 - To control the trigger, latch, and mask for the NMI input pin
 - To provide the interrupt input for the ARISC coprocessor

As this interrupt controller is not documented, information about it
comes from vendor-provided firmware blobs and from experimentation.

Differences from the sun4i interrupt controller appear to be:
 - It only has one or two registers of each kind (max 32 or 64 IRQs)
 - Multiplexing logic is added to support additional inputs
 - There is no FIQ-related logic
 - There is no interrupt priority logic

In order to fulfill its two purposes, this hardware block combines four
types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
pending" output from this chip, if enabled, is then routed to a SPI IRQ
input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect
the NMI IRQ seen at the GIC.

The NMI is followed by a contiguous block of 15 "direct" (my name for
them) IRQ inputs that are connected in parallel to both R_INTC and the
GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the
IRQs seen at the GIC.

Following the direct IRQs are the ARISC's copy of banked IRQs for shared
peripherals. These are not relevant to Linux. The remaining IRQs are
connected to a multiplexer and provide access to the first (up to) 128
SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs.

Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
a perfect scenario for using a stacked irqchip driver. We want to hook
into setting the NMI trigger type, but not actually handle any IRQ here.

To allow access to all multiplexed IRQs, this driver requires a new
binding where the interrupt number matches the GIC interrupt number.
(This moves the NMI from number 0 to 32 or 96, depending on the SoC.)
For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.

Since R_INTC is in the always-on power domain, and its output is visible
to the power management coprocessor, a stacked irqchip driver provides a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.

This commit mostly reverts commit 173bda53b3 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org
2021-01-21 20:21:49 +00:00
Arnd Bergmann 5c1ea0d842 irqchip: Remove sirfsoc driver
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210120133008.2421897-3-arnd@kernel.org
2021-01-21 20:21:41 +00:00
Arnd Bergmann 00e772c492 irqchip: Remove sigma tango driver
The tango platform is getting removed, so the driver is no
longer needed.

Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210120133008.2421897-2-arnd@kernel.org
2021-01-21 20:21:23 +00:00
Vineet Gupta 04e7f423f4 drivers/irqchip: Remove EZChip NPS interrupt controller
NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/20201105212210.1891598-3-vgupta@synopsys.com
2020-12-11 14:47:50 +00:00
Linus Torvalds e731f3146f ARM: SoC platform updates
SoC changes, a substantial part of this is cleanup of some of the older
 platforms that used to have a bunch of board files. In particular:
 
  - Removal of non-DT i.MX platforms that haven't seen activity in years,
    it's time to remove them.
  - A bunch of cleanup and removal of platform data for TI/OMAP platforms,
    moving over to genpd for power/reset control (yay!)
  - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
    closer to multiplatform support (not quite there yet, but getting
    close).
 
 THere are a few other changes too, smaller fixlets, etc. For new
 platform support, the primary ones re:
 
  - New SoC: Hisilicon SD5203, ARM926EJ-S platform.
  - Cpufreq support for i.MX7ULP
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TT4gPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx322MP/1mI56SyOFx30AqtWBPSjHJp+DzhOObyb4vD
 ndYuicBIn9tJwvVRBBZkfsbIU8EENVwrN3hOpesaj9L7xiqOqKakcnyC1REYmpIs
 8XBDfdZzy5PrMHIu3fF1ZDCQyO7KndGf5DfLVxJtcf1tSPQyQCuIA3FtS6d8Bxnz
 r491+om67ucnlFD5X0Spm3RdZH+ECmXx2iXwoS0Zi7P+X+S+ovG8wBV/X0ggeoBc
 Zgi4W01SiRupmSVZ6PA7FvWaLGQErQAALQOcFtMcFgjeWzc1v2QzcURELH8JW7ro
 72AH9st1Kvi3hoN2HNNzUnNUdQvZ+AdH8skMIpN/e1cBYqYStAF3gm/R9h+iVHbG
 GMmgzXHAFErfAW2UcF8tq1CzvQ5ChcTLNXdeoa8CeQbcDfocF3EyuKSPuDH+ve0H
 kk4tPesTAc6XCEVwLaGnoC75sdum5mSi8h9vqhln2KCdeTY7jxzH9YGHjm71Supb
 kV9vqo5Q5U/c5l2nU4r5q/DZdIahKsk3HIQZ0iG7BifAzamaTh4uyLVjtM6HSwNz
 tdHZaxoHd/PLI5IoeggFelx6qgvK5qVRLP0evgOdTLRFLj/ZbrOf0Q7DjdTy2BjZ
 Lgq461QqNapOzxq43G2IDT2+P62Q1+d+YLCKBgaGQaJicyU5m9STCNo3UBb1qH1h
 W6UwGF5z
 =0+Ee
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Olof Johansson:
 "SoC changes, a substantial part of this is cleanup of some of the
  older platforms that used to have a bunch of board files.

  In particular:

   - Remove non-DT i.MX platforms that haven't seen activity in years,
     it's time to remove them.

   - A bunch of cleanup and removal of platform data for TI/OMAP
     platforms, moving over to genpd for power/reset control (yay!)

   - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
     closer to multiplatform support (not quite there yet, but getting
     close).

  There are a few other changes too, smaller fixlets, etc. For new
  platform support, the primary ones are:

   - New SoC: Hisilicon SD5203, ARM926EJ-S platform.

   - Cpufreq support for i.MX7ULP"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
  ARM: mstar: Select MStar intc
  ARM: stm32: Replace HTTP links with HTTPS ones
  ARM: debug: add UART early console support for SD5203
  ARM: hisi: add support for SD5203 SoC
  ARM: omap3: enable off mode automatically
  clk: imx: imx35: Remove mx35_clocks_init()
  clk: imx: imx31: Remove mx31_clocks_init()
  clk: imx: imx27: Remove mx27_clocks_init()
  ARM: imx: Remove unused definitions
  ARM: imx35: Retrieve the IIM base address from devicetree
  ARM: imx3: Retrieve the AVIC base address from devicetree
  ARM: imx3: Retrieve the CCM base address from devicetree
  ARM: imx31: Retrieve the IIM base address from devicetree
  ARM: imx27: Retrieve the CCM base address from devicetree
  ARM: imx27: Retrieve the SYSCTRL base address from devicetree
  ARM: s3c64xx: bring back notes from removed debug-macro.S
  ARM: s3c24xx: fix Wunused-variable warning on !MMU
  ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
  MAINTAINERS: mark linux-samsung-soc list non-moderated
  ARM: imx: Remove remnant board file support pieces
  ...
2020-10-24 10:33:08 -07:00
Linus Torvalds 1a31c12371 - New Drivers
- Add support for initialising shared (between children) Regmaps
    - Add support for Kontron SL28CPLD
    - Add support for ENE KB3930 Embedded Controller
    - Add support for Intel FPGA PAC MAX 10 BMC
 
  - New Device Support
    - Add support for Power to Ricoh RN5T618
    - Add support for UART to Intel Lakefield
    - Add support for LP87524_Q1 to Texas Instruments LP87565
 
  - New Functionality
    - Device Tree; ene-kb3930, sl28cpld, syscon, lp87565, lp87524-q1
    - Use new helper dev_err_probe(); madera-core, stmfx, wcd934x
    - Use new GPIOD API; dm355evm_msp
    - Add wake-up capability; sprd-sc27xx-spi
    - Add ACPI support; kempld-core
 
  - Fix-ups
    - Trivial (spelling/whitespace); Kconfig, ab8500
    - Fix for unused variables; khadas-mcu, kempld-core
    - Remove unused header file(s); mt6360-core
    - Use correct IRQ flags in docs; act8945a, gateworks-gsc, rohm,bd70528-pmic
    - Add COMPILE_TEST support; asic3, tmio_core
    - Add dependency on I2C; SL28CPLD
 
  - Bug Fixes
    - Fix memory leak(s); sm501
    - Do not free regmap_config's 'name' until exit; syscon
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAl+GrSsACgkQUa+KL4f8
 d2FQ/w//TRSwPbXdUl+rYaDVQ9YwEk5Zi2U8EYBP8OGsKLjXs9GFkiuyQ5GwsoAd
 oD5N4Fh/QGxmdWafKXB96e/D+n4uFOOIWGCmNsE5NmvnWbjk1Jss4K4qV4IbUEW/
 KWxUCKPhaNcs7Vj9nfN5jItCPBaG6bQJ3qgFwZHSMhe/Su4izUYlLCfhhVAFkq1k
 oF2TgJCllqPl7ZY+VxDPD5ZWIBhV+NZoFVRFQ7Kvw1elmE+///nrfuii261G+iBm
 kHi3PtcRMDW0+Uo8B9I9xtLVUrfBMtm9ThOrn8JYLOaJ7RzWwwF6WayAKsNbDuDB
 CiYKHDZWS72IxfW3KfHk1AvbsUMJQX1kmDJ6lAhXHa3E55nGbX+U2FwgMnczJUuM
 7BzfD9pXp3nnfTQ6ZJtr1vGPLz3Nk7hcRlg9r+6TObIjzB+KNW/hyCYur7sX1Mbb
 wn3EZo5WhKnlcqrGhh3H0/kJDbHTIFDfNt80+bjLfIeKCQj1x6cByPWC7N6Ln4GC
 BDky88fb/Y9Q5bnvyEQDR16+QMpG3ko5lIUwt9Gtbhtt3/zjxzElxRlsq6u9scrp
 vZnnjqxSQ/9cvnwOsGMG+E8uVjZ+5lQu6Qi+0w20M4MX28hXLPQbpjAK/3uqH7Kz
 NLwiZe4dzRtVbAQ83ozGArTgvH9YZ5VOw/ieqk0aRf6mIExrENk=
 =1wSH
 -----END PGP SIGNATURE-----

Merge tag 'mfd-next-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Drivers:
   - Add support for initialising shared (between children) Regmaps
   - Add support for Kontron SL28CPLD
   - Add support for ENE KB3930 Embedded Controller
   - Add support for Intel FPGA PAC MAX 10 BMC

  New Device Support:
   - Add support for Power to Ricoh RN5T618
   - Add support for UART to Intel Lakefield
   - Add support for LP87524_Q1 to Texas Instruments LP87565

  New Functionality:
   - Device Tree; ene-kb3930, sl28cpld, syscon, lp87565, lp87524-q1
   - Use new helper dev_err_probe(); madera-core, stmfx, wcd934x
   - Use new GPIOD API; dm355evm_msp
   - Add wake-up capability; sprd-sc27xx-spi
   - Add ACPI support; kempld-core

  Fix-ups:
   - Trivial (spelling/whitespace); Kconfig, ab8500
   - Fix for unused variables; khadas-mcu, kempld-core
   - Remove unused header file(s); mt6360-core
   - Use correct IRQ flags in docs; act8945a, gateworks-gsc, rohm,bd70528-pmic
   - Add COMPILE_TEST support; asic3, tmio_core
   - Add dependency on I2C; SL28CPLD

  Bug Fixes:
   - Fix memory leak(s); sm501
   - Do not free regmap_config's 'name' until exit; syscon"

* tag 'mfd-next-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (34 commits)
  mfd: kempld-core: Fix unused variable 'kempld_acpi_table' when !ACPI
  mfd: sl28cpld: Depend on I2C
  mfd: asic3: Build if COMPILE_TEST=y
  dt-bindings: mfd: Correct interrupt flags in examples
  mfd: Add ACPI support to Kontron PLD driver
  mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC
  mfd: lp87565: Add LP87524-Q1 variant
  dt-bindings: mfd: Add LP87524-Q1
  dt-bindings: mfd: lp87565: Convert to yaml
  mfd: mt6360: Remove unused include <linux/version.h>
  mfd: sm501: Fix leaks in probe()
  mfd: syscon: Don't free allocated name for regmap_config
  dt-bindings: mfd: syscon: Document Exynos3 and Exynos5433 compatibles
  dt-bindings: mfd: syscon: Merge Samsung Exynos Sysreg bindings
  dt-bindings: mfd: ab8500: Remove weird Unicode characters
  mfd: sprd: Add wakeup capability for PMIC IRQ
  mfd: intel-lpss: Add device IDs for UART ports for Lakefield
  mfd: dm355evm_msp: Convert LEDs to GPIO descriptor table
  mfd: wcd934x: Simplify with dev_err_probe()
  mfd: stmfx: Simplify with dev_err_probe()
  ...
2020-10-14 15:56:58 -07:00
Marc Zyngier 63ea38a402 Merge branch 'irq/mstar' into irq/irqchip-next
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-10-10 12:46:54 +01:00
Mark-PK Tsai ad4c938c92 irqchip/irq-mst: Add MStar interrupt controller support
Add MStar interrupt controller support using hierarchy irq
domain.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Daniel Palmer <daniel@thingy.jp>
Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
2020-10-10 12:39:27 +01:00
Marc Zyngier 9b64efa837 Merge branch 'irq/ipi-as-irq', remote-tracking branches 'origin/irq/dw' and 'origin/irq/owl' into irq/irqchip-next
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-09-28 11:36:40 +01:00
Cristian Ciocaltea 27e9e554b0 irqchip: Add Actions Semi Owl SIRQ controller
This interrupt controller is found in the Actions Semi Owl SoCs (S500,
S700 and S900) and provides support for handling up to 3 external
interrupt lines.

Each line can be independently configured as interrupt and triggers on
either of the edges or either of the levels. Additionally, each line
can also be masked individually.

Co-developed-by: Parthiban Nallathambi <pn@denx.de>
Co-developed-by: Saravanan Sekar <sravanhome@gmail.com>
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1a010ef0eb78831b5657d74a0fcdef7a8efb2ec4.1600114378.git.cristian.ciocaltea@gmail.com
2020-09-25 16:57:33 +01:00
Michael Walle 03ac990e0a irqchip: Add sl28cpld interrupt controller support
Add support for the interrupt controller inside the sl28 CPLD management
controller.

The interrupt controller can handle at most 8 interrupts and is really
simplistic and consists only of an interrupt mask and an interrupt
pending register.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-09-17 15:58:37 +01:00
Grzegorz Jaszczyk 04e2d1e069 irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts
The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
interrupt controller (INTC) that can handle various system input events
and post interrupts back to the device-level initiators. The INTC can
support upto 64 input events with individual control configuration and
hardware prioritization. These events are mapped onto 10 output interrupt
lines through two levels of many-to-one mapping support. Different
interrupt lines are routed to the individual PRU cores or to the host
CPU, or to other devices on the SoC. Some of these events are sourced
from peripherals or other sub-modules within that PRUSS, while a few
others are sourced from SoC-level peripherals/devices.

The PRUSS INTC platform driver manages this PRUSS interrupt controller
and implements an irqchip driver to provide a Linux standard way for
the PRU client users to enable/disable/ack/re-trigger a PRUSS system
event. The system events to interrupt channels and output interrupts
relies on the mapping configuration provided either through the PRU
firmware blob (for interrupts routed to PRU cores) or via the PRU
application's device tree node (for interrupt routed to the main CPU).
In the first case the mappings will be programmed on PRU remoteproc
driver demand (via irq_create_fwspec_mapping) during the boot of a PRU
core and cleaned up after the PRU core is stopped.

Reference counting is used to allow multiple system events to share a
single channel and to allow multiple channels to share a single host
event.

The PRUSS INTC module is reference counted during the interrupt
setup phase through the irqchip's irq_request_resources() and
irq_release_resources() ops. This restricts the module from being
removed as long as there are active interrupt users.

The driver currently supports and can be built for OMAP architecture
based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
All of these SoCs support 64 system events, 10 interrupt channels and
10 output interrupt lines per PRUSS INTC with a few SoC integration
differences.

NOTE:
Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
enables multiple external events to be routed to a specific number
of input interrupt events. Any non-default external interrupt event
directed towards PRUSS needs this crossbar to be setup properly.

Co-developed-by: Suman Anna <s-anna@ti.com>
Co-developed-by: Andrew F. Davis <afd@ti.com>
Co-developed-by: Roger Quadros <rogerq@ti.com>
Co-developed-by: David Lechner <david@lechnology.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-09-17 12:20:31 +01:00
Arnd Bergmann 95b415efff ARM: s3c24xx: move irqchip driver back into platform
It was a good idea to move it out at first, but the irqchip code
is still tightly connected to the s3c24xx platform code and uses
multiple internal header files, so just move it back for the
time being to avoid those dependencies.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-21-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-08-19 21:40:52 +02:00
Anup Patel 6b7ce8927b
irqchip: RISC-V per-HART local interrupt controller driver
The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.

We add a driver for the RISC-V local interrupt controller, which
eventually replaces the RISC-V architecture code, allowing for a
better split between arch code and drivers.

The driver is compliant with RISC-V Hart-Level Interrupt Controller
DT bindings located at:
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
[Palmer: Cleaned up warnings]
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2020-06-09 19:11:21 -07:00
Jiaxun Yang 632dcc2c75 irqchip: Add Loongson PCH MSI controller
This controller appears on Loongson LS7A family of PCH to transform
interrupts from PCI MSI into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.yang@flygoat.com
2020-05-29 09:42:18 +01:00
Jiaxun Yang ef8c01eb64 irqchip: Add Loongson PCH PIC controller
This controller appears on Loongson LS7A family of PCH to transform
interrupts from devices into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.yang@flygoat.com
2020-05-29 09:42:18 +01:00
Jiaxun Yang 818e915fba irqchip: Add Loongson HyperTransport Vector support
This controller appears on Loongson-3 chips for receiving interrupt
vectors from PCH's PIC and PCH's PCIe MSI interrupts.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200528152757.1028711-2-jiaxun.yang@flygoat.com
2020-05-29 09:42:18 +01:00
Jiaxun Yang a93f1d903f irqchip: Add driver for Loongson-3 HyperTransport PIC controller
This controller appeared on Loongson-3 family of chips to receive
interrupts from PCH PIC.
It is a I8259 with optimized interrupt polling flow. We can poll
interrupt number from HT vector directly but still have to follow
standard I8259 routines to mask, unmask and EOI.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-03-25 10:56:43 +01:00
Jiaxun Yang dbb1522679 irqchip: Add driver for Loongson I/O Local Interrupt Controller
This controller appeared on Loongson family of chips as the primary
package interrupt source.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-03-25 10:53:47 +01:00
Joakim Zhang 2fbb13961e irqchip: Add NXP INTMUX interrupt multiplexer support
The Interrupt Multiplexer (INTMUX) expands the number of peripherals
that can interrupt the core:
* The INTMUX has 8 channels that are assigned to 8 NVIC interrupt slots.
* Each INTMUX channel can receive up to 32 interrupt sources and has 1
  interrupt output.
* The INTMUX routes the interrupt sources to the interrupt outputs.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200117060653.27485-3-qiangqing.zhang@nxp.com
2020-01-20 19:10:05 +00:00
Hyunki Koo b74416dba3 irqchip: Define EXYNOS_IRQ_COMBINER
This patch is written to clean up dependency of ARCH_EXYNOS
Not all exynos device have IRQ_COMBINER, especially aarch64 EXYNOS
but it is built for all exynos devices.
Thus add the config for EXYNOS_IRQ_COMBINER
remove direct dependency between ARCH_EXYNOS and exynos-combiner.c
and only selected on the aarch32 devices

Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20191224211108.7128-1-hyunki00.koo@gmail.com
2020-01-20 19:10:05 +00:00
Eddie James 04f605906f irqchip: Add Aspeed SCU interrupt controller
The Aspeed SOCs provide some interrupts through the System Control
Unit registers. Add an interrupt controller that provides these
interrupts to the system.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/1579123790-6894-3-git-send-email-eajames@linux.ibm.com
2020-01-20 19:10:04 +00:00
Rasmus Villemoes 0dcd9f8727 irqchip: Add support for Layerscape external interrupt lines
The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.

In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.

Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.

Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.

Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
2019-11-10 18:47:49 +00:00
Paul Cercueil 9536eba03e
irqchip: Add irq-ingenic-tcu driver
This driver handles the interrupt controller built in the Timer/Counter
Unit (TCU) of the JZ47xx SoCs from Ingenic.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
2019-08-08 15:30:07 -07:00
Talel Shenhar 1eb77c3bcd irqchip/al-fic: Introduce Amazon's Annapurna Labs Fabric Interrupt Controller Driver
The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs.
A FIC (Fabric Interrupt Controller) may be cascaded into another FIC or
directly to the main CPU Interrupt Controller (e.g. GIC).

Signed-off-by: Talel Shenhar <talel@amazon.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-07-03 09:19:11 +01:00
Geert Uytterhoeven a644ccb819 irqchip: Add Renesas RZ/A1 Interrupt Controller driver
Add a driver for the Renesas RZ/A1 Interrupt Controller.

This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.

NMI edge select is not yet supported.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29 10:42:25 +01:00
Linus Torvalds d9351ea14d Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull IRQ chip updates from Ingo Molnar:
 "A late irqchips update:

   - New TI INTR/INTA set of drivers

   - Rewrite of the stm32mp1-exti driver as a platform driver

   - Update the IOMMU MSI mapping API to be RT friendly

   - A number of cleanups and other low impact fixes"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits)
  iommu/dma-iommu: Remove iommu_dma_map_msi_msg()
  irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg()
  irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg()
  irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg()
  irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg()
  iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts
  genirq/msi: Add a new field in msi_desc to store an IOMMU cookie
  arm64: arch_k3: Enable interrupt controller drivers
  irqchip/ti-sci-inta: Add msi domain support
  soc: ti: Add MSI domain bus support for Interrupt Aggregator
  irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver
  dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
  irqchip/ti-sci-intr: Add support for Interrupt Router driver
  dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
  gpio: thunderx: Use the default parent apis for {request,release}_resources
  genirq: Introduce irq_chip_{request,release}_resource_parent() apis
  firmware: ti_sci: Add helper apis to manage resources
  firmware: ti_sci: Add RM mapping table for am654
  firmware: ti_sci: Add support for IRQ management
  firmware: ti_sci: Add support for RM core ops
  ...
2019-05-19 10:58:45 -07:00
Lokesh Vutla 9f1463b86c irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver
Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator
which is an interrupt controller that does the following:
- Converts events to interrupts that can be understood by
  an interrupt router.
- Allows for multiplexing of events to interrupts.

Configuration of the interrupt aggregator registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol. Add the required infrastructure to
allow the allocation and routing of these events.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-01 10:49:13 +01:00
Lokesh Vutla cd844b0715 irqchip/ti-sci-intr: Add support for Interrupt Router driver
Texas Instruments' K3 generation SoCs has an IP Interrupt Router
that does allows for redirection of input interrupts to host
interrupt controller. Interrupt Router inputs are either from a
peripheral or from an Interrupt Aggregator which is another
interrupt controller.

Configuration of the interrupt router registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.

Add support for Interrupt Router driver over TISCI protocol.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-01 10:48:56 +01:00
Linus Walleij 5b978c1066 irqchip: Add driver for IXP4xx
The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale
platform that has very wide deployment and use.

As part of modernizing the platform, we need to implement a
proper irqchip in the irqchip subsystem.

The IXP4xx irqchip is tightly jotted together with the GPIO
controller, and whereas in the past we would deal with this
complex logic by adding necessarily different code, we can
nowadays modernize it using a hierarchical irqchip.

The actual IXP4 irqchip is a simple active low level IRQ
controller, whereas the GPIO functionality resides in a
different memory area and adds edge trigger support for
the interrupts.

The interrupts from GPIO lines 0..12 are 1:1 mapped to
a fixed set of hardware IRQs on this IRQchip, so we
expect the child GPIO interrupt controller to go in and
allocate descriptors for these interrupts.

For the other interrupts, as we do not yet have DT
support for this platform, we create a linear irqdomain
and then go in and allocate the IRQs that the legacy
boards use. This code will be removed on the DT probe
path when we add DT support to the platform.

We add some translation code for supporting DT
translations for the fwnodes, but we leave most of that
for later.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:50 +02:00
Linus Torvalds afe6fe7036 ARM: SoC: late updates for linux-5.1
Here are two branches that came relatively late during the linux-5.0
 development cycle and have dependencies on the other branches:
 
 - On the TI OMAP platform, the CPSW Ethernet PHY mode selection driver
   is being replaced, this puts the final pieces in place
 
 - On the DaVinci platform, the interrupt handling code in arch/arm
   gets moved into a regular device driver in drivers/irqchip.
 
 Since they both had some time in linux-next after the 5.0-rc8
 release, I'm sending them along with the other updates.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJcf9ZXAAoJEGCrR//JCVIn4NgP/0Q0+qP1QTmc/XL1yzSKhemg
 PVu42+EtoR/tyaTu+spf/aQyJiC/1E9NE7n9r9FvQqpxxlipv6XLxZbti89C83mL
 Ynk2D3Z2FjDZvVSl7WdgX9J/GoaJPXefTkfUr4ZZtcMNhLOCl2ATOO6ytuAXid7Q
 keTfHKI2rwUWFmu+ojGuONdyM3BA12hEYNH+B12rnXAcy8ylb70XMxitPx5JGkJX
 ZdhG58tGNM3EDdQh7mornlFA17IUqrYpt/daIBDZaPwwz3P8+vkMTl10IkEsvIcA
 soMmiAp75jYlnLec8A9awGFBzPznzxH7a9PdvPByW044kARSgfFDRbijmwAij6oA
 CHCEmmFP9LOm9zP8qqC0lsfwOBOnSL8b7pFXL2jTJQO897hfBLQSUTVFQ8K3Sznx
 p8CCv++YU2ZQT6rGg7qRIApvfjNtRimBykCyy0Nh03MDUUgNosfqff8EvSXMbsbs
 BwjBavM1QhF2E6trKrxEi3n3+WrHK1JjVL0JxP2rQlraifRrSUXQglqiAOXl4mN7
 GRIjwI5WYeRKMj7nqgj10MO/GBbDAmME482U2+0RvEX2pm/wUiVQjm/6zWOp5Be/
 cAcH61hEXxQbTXh0aVmzSKUHuFVCGl2FC75/JWVzRosdmval7C1MgILiucrXKUVe
 hhF12S1z45yfZRwY7sVD
 =0u1N
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC late updates from Arnd Bergmann:
 "Here are two branches that came relatively late during the linux-5.0
  development cycle and have dependencies on the other branches:

   - On the TI OMAP platform, the CPSW Ethernet PHY mode selection
     driver is being replaced, this puts the final pieces in place

   - On the DaVinci platform, the interrupt handling code in arch/arm
     gets moved into a regular device driver in drivers/irqchip.

  Since they both had some time in linux-next after the 5.0-rc8 release,
  I'm sending them along with the other updates"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver
  ARM: davinci: remove intc related fields from davinci_soc_info
  irqchip: davinci-cp-intc: move the driver to drivers/irqchip
  ARM: davinci: cp-intc: remove redundant comments
  ARM: davinci: cp-intc: drop GPL license boilerplate
  ARM: davinci: cp-intc: use readl/writel_relaxed()
  ARM: davinci: cp-intc: unify error handling
  ARM: davinci: cp-intc: improve coding style
  ARM: davinci: cp-intc: request the memory region before remapping it
  ARM: davinci: cp-intc: use the new-style config structure
  ARM: davinci: cp-intc: convert all hex numbers to lowercase
  ARM: davinci: cp-intc: use a common prefix for all symbols
  ARM: davinci: cp-intc: add the new config structures for da8xx SoCs
  irqchip: davinci-cp-intc: add a new config structure
  ARM: davinci: cp-intc: add a wrapper around cp_intc_init()
  ARM: davinci: cp-intc: remove cp_intc.h
  irqchip: davinci-aintc: move the driver to drivers/irqchip
  ARM: davinci: aintc: remove unnecessary includes
  ARM: davinci: aintc: remove the timer-specific irq_set_handler()
  ARM: davinci: aintc: request memory region before remapping it
  ...
2019-03-06 10:22:26 -08:00
Bartosz Golaszewski 0fc3d74cf9 irqchip: davinci-cp-intc: move the driver to drivers/irqchip
The cp-intc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-19 20:03:42 +05:30
Bartosz Golaszewski 0145beed9d irqchip: davinci-aintc: move the driver to drivers/irqchip
The aintc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs. There's no device-tree support for any dm* board so
there's no IRQCHIP_OF_DECLARE() - there's only the exported init
function called from machine code.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-19 20:02:17 +05:30
Jiaxun Yang 9e543e22e2 irqchip: Add driver for Loongson-1 interrupt controller
This controller appeared on Loongson-1 family MCUs
including Loongson-1B and Loongson-1C.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-02-14 10:34:18 +00:00
Lucas Stach 0136afa089 irqchip: Add driver for imx-irqsteer controller
The irqsteer block is a interrupt multiplexer/remapper found on the
i.MX8 line of SoCs.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-18 15:37:22 +00:00
Richard Fitzgerald da0abe1a04 irqchip: Add driver for Cirrus Logic Madera codecs
The Cirrus Logic Madera codecs (Cirrus Logic CS47L35/85/90/91 and WM1840)
are highly complex devices containing up to 7 programmable DSPs and many
other internal sources of interrupts plus a number of GPIOs that can be
used as interrupt inputs. The large number (>150) of internal interrupt
sources are managed by an on-board interrupt controller.

This driver provides the handling for the interrupt controller. As the
codec is accessed via regmap, we can make use of the generic IRQ
functionality from regmap to do most of the work. Only around half of
the possible interrupt source are currently of interest from the driver
so only this subset is defined. Others can be added in future if needed.

The KConfig options are not user-configurable because this driver is
mandatory so is automatically included when the parent MFD driver is
selected.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-18 14:06:56 +00:00
Manivannan Sadhasivam d852e62ad6 irqchip: Add RDA8810PL interrupt driver
Add interrupt driver for RDA Micro RDA8810PL SoC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-13 09:35:57 +00:00
Linus Torvalds ac43507589 This tag contains the Linux port for C-SKY(csky) based on linux-4.19
Release, which has been through 10 rounds of review on mailing list.
 
 We almost got the Acked-by/Reviewed-by of all patches except "Process
 management and Signal", but all've been tested.
 
 Here is the LTP-20180118 test report:
 -----------------------------------------------
 Total Tests: 1298
 Total Skipped Tests: 281
 Total Failures: 10
 Kernel Version: 4.19.0+
 Machine Architecture: csky
 Hostname: buildroot
 -----------------------------------------------
 
 This patchset adds architecture support to Linux for C-SKY's 32-bit embedded
 
 There are two ABI versions with several CPU cores in this patchset:
   ABIv1: 610 (16-bit instruction, 32-bit data path, VIPT Cache ...)
   ABIv2: 807 810 860 (16/32-bit variable length instruction, PIPT Cache,
 	 SMP ...)
 
 More information: http://en.c-sky.com
 The development repo: https://github.com/c-sky/csky-linux
 ABI Documentation: https://github.com/c-sky/csky-doc
 
 Here is the pre-built cross compiler for fast test from our CI:
 https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz
 
 We use buildroot as our CI-test enviornment. "LTP, Lmbench ..."
 will be tested for every commit. See here for more details:
 https://gitlab.com/c-sky/buildroot/pipelines
 
 We'll continouslly improve csky subsystem in future.
 
 Changes in v10:
  - Remove duplicated headers in asm/Kbuild and uapi/asm/Kbuild.
  - Change to (__NR_arch_specific_syscall + 1) in unistd.h.
  - Drop dword access for get_user_size patch.
  - Involve the interrupt controller drivers after got Reviewed-by.
 
 Changes in v9:
  - Remove unused code in smp.c and use per_cpu for ipi_data.
  - Fixup r15 register access in abiv1/alignment.c.
  - Improve the changelog comment in commit-msg.
 
 Changes in v8:
  - Pass make allmodconfig.
  - Implement abiv1 get_user_dword().
  - Remove set_irq_mapping() used by driver in smp.c.
 
 Changes in v7:
  - Use checkpatch.pl to check all patches and fixup as possible.
  - Remove github.com/c-sky print in bootup.
  - Give a return in DMA_ATTR_NON_CONSISTENT in csky_dma_alloc_atomic().
  - Remove the NSIGXXX in fpu.c and use force_sig_fault() in fpu.c.
  - Remove irq.h and add it in asm/Kbuild.
  - Use byteswap helpers in abiv1/bswapXi.c.
  - Fixup arch_sync_dma() only with one page problem.
 
 Changes in v6:
  - use asm-generic/bitops/atomic.h for all in asm/bitops.h
  - fix flush_cache_range and tlb_start_vma
  - fix compile error with include linux/bug.h in cmpxchg.h
  - improve the comment
 
 Changes in v5:
  - remove redundant smp_mb operations in spinlock.h
  - add commit message for dt-bindings docs
  - add CPUHP_AP_CSKY_TIMER_STARTING in hotplug.h for csky_mptimer
  - add COMPILE_TEST for timer-gx6605s Kconfig
  - seperate csky two interrupt controllers with 2 patches
  - add MAINTAINERS patch for csky
  - move IPI_IRQ into csky_mptimer, fixup irq_mapping problem
  - coding convension
 
 Changes in v4:
  - cleanup defconfig
  - use ksys_ in syscall.c
  - remove wrong comment in vdso.c
  - Use GENERIC_IRQ_MULTI_HANDLER
  - optimize the memset.c
  - fixup dts warnings
  - remove big-endian in byteorder.h
 
 Changes in v3:
 dc560f1 csky: change to EM_CSKY 252 for elf.h
 2ac3ddf csky: remove gx6605s.dts
 af00b8c csky: add defconfig and qemu.dts
 6c87efb csky: remove the deprecate name.
 f6dda39 csky: add dt-bindings doc.
 d9f02a8 csky: remove KERNEL_VERSION in upstream branch
 7bd663c csky: Use kernel/dma/noncoherent.c
 1544c09 csky: bugfix emmc hang up LINS-976
 e963271 csky: cleanup include/asm/Kbuild
 cd267ba csky: remove CSKY_DEBUG_INFO
 78950da csky: remove dcache invalid.
 13fe51d csky: remove csum_ipv6_magic(), use generic one.
 a7372db csky: bugfix CK810 access twice error.
 1bb7c69 csky: bugfix add gcc asm memory for barrier.
 5ea3257 csky: add -msoft-float instead of -mfloat-abi=soft.
 38b037d csky: bugfix losing cache flush range.
 ab5e8c4 csky: Add ticket-spinlock and qrwlock support.
 c9aaec5 csky: rename cskyksyms.c to libgcc_ksyms.c
 28c5e48 csky: avoid the MB on failure: trylock
 f929c97 csky: bugfix idly4 may cause exception.
 09dc496 csky: Use GENERIC_ASHLDI3/ASHRDI3 etc
 6ecc99d csky: optimize smp boot code.
 16f50df csky: asm/bug.h simple implement.
 0ba532a csky: csky asm/atomic.h added.
 df66947 csky: asm/compat.h added
 275a06f csky: String operations optimization
 4c021dd csky: ck860 SMP memory barrier optimize
 fc39c66 csky: Add wait/doze/stop
 d005144 csky: add GENERIC_ALLOCATOR
 4a10074 csky: bugfix cma failed for highmem.
 9f2ca70 csky: CMA supported :)
 53791f4 csky: optimize csky_dma_alloc_nonatomic
 974676e csky: optimize the cpuinfo printf.
 2538669 csky: bugfix make headers_install error.
 1158d0c csky: prevent hard-float and vdsp instructions.
 dc3c856 csky: increase Normal Memory to 1GB
 6ee5932 csky: bugfix qemu mmu couldn't support 0xffffe000
 1d7dfb8 csky: csky_dma_alloc_atomic added.
 caf6610 csky: restruct the fixmap memory layout.
 5a17eaa csky: use -Wa,-mcpu=ckxxxfv to the as.
 4d51829 csky: use Kconfig.hz.
 f3f88fa csky: BUGFIX add -mcpu=ck860f support
 6192fd1 csky: support ck860 fpu.
 7aa5e01 csky: BUGFIX add smp_mb before ldex.
 15758e2 csky: BUGFIX tlbi couldn't handle ASID in another CPU core.
 d69640d csky: enable tlbi.vas to flush one tlb entry
 
 Changes in v2:
 a29bfc8 csky: add pre_mmu_init, move misc mmu setup to mm/init.c
 4eab702 csky: no need kmap for !VM_EXEC.
 6770eec csky: Use TEE as the name of CPU Trusted Execution Enviornment.
 a56c8c7 csky: update the cache flush api.
 1a48a95 csky: add C-SKY Trust Zone.
 b7a0a44 csky: use CONFIG_RAM_BASE as the same in memory of dts.
 15adf81 csky: remove unused code.
 35c0d97 csky: bugfix lost a cacheline flush when start isn't cacheline-aligned.
 4e82c8d csky: use tlbi.alls for ck860 smp temporary.
 ae7149e csky: bugfix use kmap_atomic() to prevent no mapped addr.
 5538795 csky: bugfix user access in kernel space.
 a7aa591 csky: add 16bit user space bkpt.
 0de70ec csky: add sync.is for cmpxchg in SMP.
 c5c08a1 csky: seperate sync.is and sync for SMP and Non-SMP.
 dbbf4dc csky: use sync.is for ck860 mb().
 f33f8da csky: rewrite the alignment implement.
 68152c7 csky: bugfix alignment pt_regs error.
 d618d43 csky: support set_affinity for irq balance in SMP
 ebf86c9 csky: bugfix compile error without CONFIG_SMP.
 8537eea csky: remove debug code.
 4ebc051 csky: bugfix compile error with linux-4.9.56
 75a938e csky: C-SKY SMP supported.
 0eebc07 csky: use internal function for map_sg.
 3d29751 csky: bugfix can't support highmem
 b545d2a csky: bugfix r26 is the link reg for jsri_to_jsr.
 9e3313a csky: bugfix sync tls for abiv1 in ptrace.
 587a0d2 csky: use __NR_rt_sigreturn in asm-generic.
 f562b46 csky: bugfix gpr_set & fpr_set
 f57266f csky: bugfix fpu_fpe_helper excute mtcr mfcr.
 c676669 csky: bugfix ave is default enable on reset.
 d40d34d csky: remove unused sc_mask in sigcontext.h.
 274b7a2 csky: redesign the signal's api
 7501771 csky: bugfix forget restore usp.
 923e2ca csky: re-struct the pt_regs for regset.
 2a1e499 csky: fixup config.
 ada81ec csky: bugfix abiv1 compile error.
 e34acb9 csky: bugfix abiv1 couldn't support -mno-stack-size.
 ec53560 csky: change irq map, reserve soft_irq&private_irq space.
 c7576f7 csky: bugfix modpost warning with -mno-stack-size
 c8ff9d4 csky: support csky mp timer alpha version.
 deabaaf csky: update .gitignore.
 574815c csky: bugfix compile error with abiv1 in 4.15
 0b426a7 csky: bugfix format of cpu verion id.
 083435f csky: irq-csky-v2 alpha init.
 21209e5 csky: add .gitignore
 73e19b4 csky: remove FMFS_FPU_REGS/FMTS_FPU_REGS
 07e8fac csky: add fpu regset in ptrace.c
 cac779d csky: add CSKY_VECIRQ_LEGENCY for SOC bug.
 54bab1d csky: move usp into pt_regs.
 b167422 csky: support regset for ptrace.
 a098d4c csky: remove ARCH_WANT_IPC_PARSE_VERSION
 fe61a84 csky: add timer-of support.
 27702e2 csky: bugfix boot error.
 ebe3edb csky: bugfix gx6605s boot failed  - add __HEAD to head.section for head.S  - move INIT_SECTION together to fix compile warning.
 7138cae csky: coding convension for timer-nationalchip.c
 fa7f9bb csky: use ffs instead of fls.
 ddc9e81 csky: change to generic irq chip for irq-csky.c
 e9be8b9 irqchip: add generic irq chip for irq-nationalchip
 2ee83fe csky: add set_handle_irq(), ref from openrisc & arm.
 74181d6 csky: use irq_domain_add_linear instead of leagcy.
 fa45ae4 csky: bugfix setup stroge order for uncached.
 eb8030f csky: add HIGHMEM config in Kconfig
 4f983d4 csky: remove "default n" in Kconfig
 2467575 csky: use asm-generic/signal.h
 77438e5 csky: coding conventions for irq.c
 2e4a2b4 csky: optimize the cache flush ops.
 96e1c58 csky: add CONFIG_CPU_ASID_BITS.
 9339666 csky: add cprcr() cpwcr() for abiv1
 ff05be4 csky: add THREAD_SHIFT define in asm/page.h
 52ab022 csky: add mfcr() mtcr() in asm/reg_ops.h
 bdcd8f3 csky: revert back Kconfig select.
 590c7e6 csky: bugfix compile error with CONFIG_AUDIT
 1989292 csky: revert some back with cleanup unistd.h
 f1454fe csky: cleanup unistd.h
 5d2985f csky: cleanup Kconfig and Makefile.
 423d97e csky: cancel subdirectories
 cae2af4 csky: use asm-generic/fcntl.h
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEE2KAv+isbWR/viAKHAXH1GYaIxXsFAlvT4KESHHJlbl9ndW9A
 Yy1za3kuY29tAAoJEAFx9RmGiMV7xvoP/RpZO14XK0LeKjP9DllhvxSF49iL2MxC
 GGqPpRzYvzjl6KNd8VxwUbi7VCMJd8et3FF7lIfRaLxeHgj/kqk6X3JIzFON6rom
 3dRzy5XDV1bzsaZoqRK2lysGJwVmkh+CQVpmGvdSrziFPqoHyzALF0T2ggX97lft
 HVpkg/ugiamb7a3p8U2oI5p8V05+beXgTFAqb5QszJwmPVFNaqs6CvnjmFJxJ4L8
 EAyXZ6MXjgLPE0z+0ACCkBcK66ejneTVrcGaxgNaMT5kzcE5qCF6bTZxRx7YxwnA
 tbk8q+/dd5W1pbfBff3NifXeSHvkWqn7vmTq+PqGnid/92cJTzjspjaakZgEfbTP
 F8kB5jND54hlchdKfqrfoOpi3W8UYEfqdf1BHWgqsptWpq6GoTMJJE6y6rfvy1E7
 r/F8rSKJlc8SxVa8/VIQqO4LbSlxm/wnO7sGoeYi8TjO3ZMCBIm4Had0f5uJTgdH
 WENC5WP1xyle5BsL3BJiTLQl1qappWptX44YaVod2A9HtdIOsVWCFNdhFPCis1jX
 RaoP7pHBxQ5Q6r8Nue9bBa2F3gK7IOh1EKEJ821AgA9Pz2Gm8wZ1XzsPqFCiAkkS
 PcIuZQl7l/eVoiXXEqUTQFlzL4K8WnvKCYAdRZWklGKfE0Ek5RD+KVXhqFE8Ujz4
 xa+OgEzn5cQA
 =kHer
 -----END PGP SIGNATURE-----

Merge tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux

Pull C-SKY architecture port from Guo Ren:
 "This contains the Linux port for C-SKY(csky) based on linux-4.19
  Release, which has been through 10 rounds of review on mailing list.

  More information:

    http://en.c-sky.com

  The development repo:

    https://github.com/c-sky/csky-linux

  ABI Documentation:

    https://github.com/c-sky/csky-doc

  Here is the pre-built cross compiler for fast test from our CI:

    https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz

  We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will
  be tested for every commit. See here for more details:

    https://gitlab.com/c-sky/buildroot/pipelines

  We'll continouslly improve csky subsystem in future"

Arnd acks, and adds the following notes:
 "I did a thorough review of the ABI, which as usual mainly consists of
  spotting any files that don't use the asm-generic ABI itself, and
  having it changed to it matches exactly what we do on other new
  architectures.

  I also looked at every other patch and commented on maybe half of them
  where I saw something that did not quite seem right. Others have
  reviewed specific patches in greater depth. I'm sure that one could
  fine more of the minor details, but as long as they are not ABI
  relevant, they can be fixed later.

  The only patch that is part of the ABI and that nobody reviewed is the
  signal handling. This is one of the areas I never worked on in much
  detail. I did not see anything wrong with it, but I also don't know
  what the problems with the other architectures are here, and we seem
  to be hitting issues occasionally, and we never managed to generalize
  this enough for new architectures to have a trivial implementation.

  I was originally hoping that we could have the 64-bit time_t
  interfaces ready in time to completely drop the 32-bit ones, but that
  did not happen. We might still remove them in the next merge window
  depending on whether the libc upstream people prefer to keep them or
  not.

  One more general comment: I think this may well be the last new CPU
  architecture we ever add to the kernel. Both nds32 and c-sky are made
  by companies that also work on risc-v, and generally speaking risc-v
  seems to be killing off any of the minor licensable instruction set
  projects, just like ARM has mostly killed off the custom
  vendor-specific instruction sets already.

  If we add another architecture in the future, it may instead be
  something like the LLVM bitcode or WebAssembly, who knows?"

To which Geert Uytterhoeven pipes in about another architecture still in
the pipeline: Kalray MPPA.

* tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux: (24 commits)
  dt-bindings: interrupt-controller: C-SKY APB intc
  irqchip: add C-SKY APB bus interrupt controller
  dt-bindings: interrupt-controller: C-SKY SMP intc
  irqchip: add C-SKY SMP interrupt controller
  MAINTAINERS: Add csky
  dt-bindings: Add vendor prefix for csky
  dt-bindings: csky CPU Bindings
  csky: Misc headers
  csky: SMP support
  csky: Debug and Ptrace GDB
  csky: User access
  csky: Library functions
  csky: ELF and module probe
  csky: Atomic operations
  csky: IRQ handling
  csky: VDSO and rt_sigreturn
  csky: Process management and Signal
  csky: MMU and page table management
  csky: Cache and TLB routines
  csky: System Call
  ...
2018-10-29 08:25:00 -07:00
Guo Ren edff1b4835 irqchip: add C-SKY APB bus interrupt controller
The driver is for C-SKY APB bus interrupt controller. It's a simple
interrupt controller which use pending reg to detect the irq and use
enable/disable reg to mask/unmask interrupt sources.

A lot of SOCs based on C-SKY CPU use the interrupt controller as root
controller.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
2018-10-26 00:54:30 +08:00
Guo Ren d8a5f5f791 irqchip: add C-SKY SMP interrupt controller
The driver is for C-SKY SMP interrupt controller. It support 16
soft-irqs, 16 private-irqs, and 992 max external-irqs, a total of
1024 interrupts.

C-SKY CPU 807/810/860 SMP/non-SMP could use it.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-26 00:54:29 +08:00
Miquel Raynal 61ce8d8d8a irqchip/irq-mvebu-sei: Add new driver for Marvell SEI
This is a cascaded interrupt controller in the AP806 GIC that collapses
SEIs (System Error Interrupt) coming from the AP and the CPs (through
the ICU).

The SEI handles up to 64 interrupts. The first 21 interrupts are wired
from the AP. The next 43 interrupts are from the CPs and are triggered
through MSI messages. To handle this complexity, the driver has to
declare to the upper layer: one IRQ domain for the wired interrupts,
one IRQ domain for the MSIs; and acts as a MSI controller ('parent')
by declaring an MSI domain.

Suggested-by: Haim Boot <hayim@marvell.com>
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-02 12:00:08 +01:00
Christoph Hellwig 8237f8bc4f
irqchip: add a SiFive PLIC driver
Add a driver for the SiFive implementation of the RISC-V Platform Level
Interrupt Controller (PLIC).  The PLIC connects global interrupt sources
to the local interrupt controller on each hart.

This driver is based on the driver in the RISC-V tree from Palmer Dabbelt,
but has been almost entirely rewritten since, and includes many fixes
from Atish Patra.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
[Binding update by Palmer]
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 08:31:32 -07:00
Marc Zyngier 505287525c irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller
GICv3 offers the possibility to signal SPIs using a pair of doorbells
(SETPI, CLRSPI) under the name of Message Based Interrupts (MBI).
They can be used as either traditional (edge) MSIs, or the more exotic
level-triggered flavour.

Let's implement support for platform MSI, which is the original intent
for this feature.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-8-marc.zyngier@arm.com
2018-05-13 15:59:01 +02:00
Linus Torvalds df34df483a Staging/IIO patches for 4.17-rc1
Here is the big set of Staging/IIO driver patches for 4.17-rc1.
 
 It is a lot, over 500 changes, but not huge by previous kernel release
 standards.  We deleted more lines than we added again (27k added vs. 91k
 remvoed), thanks to finally being able to delete the IRDA drivers and
 networking code.
 
 We also deleted the ccree crypto driver, but that's coming back in
 through the crypto tree to you, in a much cleaned-up form.
 
 Added this round is at lot of "mt7621" device support, which is for an
 embedded device that Neil Brown cares about, and of course a handful of
 new IIO drivers as well.
 
 And finally, the fsl-mc core code moved out of the staging tree to the
 "real" part of the kernel, which is nice to see happen as well.
 
 Full details are in the shortlog, which has all of the tiny cleanup
 patches described.
 
 All of these have been in linux-next for a while with no reported
 issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCWsSnAA8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+yn60ACgxKvU/5XBP14hBkBpAcD0Q43OHe0AniEti65M
 Kw03GWK3NNM3pzk49BjZ
 =sj3K
 -----END PGP SIGNATURE-----

Merge tag 'staging-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging/IIO updates from Greg KH:
 "Here is the big set of Staging/IIO driver patches for 4.17-rc1.

  It is a lot, over 500 changes, but not huge by previous kernel release
  standards. We deleted more lines than we added again (27k added vs.
  91k remvoed), thanks to finally being able to delete the IRDA drivers
  and networking code.

  We also deleted the ccree crypto driver, but that's coming back in
  through the crypto tree to you, in a much cleaned-up form.

  Added this round is at lot of "mt7621" device support, which is for an
  embedded device that Neil Brown cares about, and of course a handful
  of new IIO drivers as well.

  And finally, the fsl-mc core code moved out of the staging tree to the
  "real" part of the kernel, which is nice to see happen as well.

  Full details are in the shortlog, which has all of the tiny cleanup
  patches described.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'staging-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (579 commits)
  staging: rtl8723bs: Remove yield call, replace with cond_resched()
  staging: rtl8723bs: Replace yield() call with cond_resched()
  staging: rtl8723bs: Remove unecessary newlines from 'odm.h'.
  staging: rtl8723bs: Rework 'struct _ODM_Phy_Status_Info_' coding style.
  staging: rtl8723bs: Rework 'struct _ODM_Per_Pkt_Info_' coding style.
  staging: rtl8723bs: Replace NULL pointer comparison with '!'.
  staging: rtl8723bs: Factor out rtl8723bs_recv_tasklet() sections.
  staging: rtl8723bs: Fix function signature that goes over 80 characters.
  staging: rtl8723bs: Fix lines too long in update_recvframe_attrib().
  staging: rtl8723bs: Remove unnecessary blank lines in 'rtl8723bs_recv.c'.
  staging: rtl8723bs: Change camel case to snake case in 'rtl8723bs_recv.c'.
  staging: rtl8723bs: Add missing braces in else statement.
  staging: rtl8723bs: Add spaces around ternary operators.
  staging: rtl8723bs: Fix lines with trailing open parentheses.
  staging: rtl8723bs: Remove unnecessary length #define's.
  staging: rtl8723bs: Fix IEEE80211 authentication algorithm constants.
  staging: rtl8723bs: Fix alignment in rtw_wx_set_auth().
  staging: rtl8723bs: Remove braces from single statement conditionals.
  staging: rtl8723bs: Remove unecessary braces from switch statement.
  staging: rtl8723bs: Fix newlines in rtw_wx_set_auth().
  ...
2018-04-04 18:56:27 -07:00
Linus Torvalds 5b1f3dc927 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
 "The usual pile of boring changes:

   - Consolidate tasklet functions to share code instead of duplicating
     it

   - The first step for making the low level entry handler management on
     multi-platform kernels generic

   - A new sysfs file which allows to retrieve the wakeup state of
     interrupts.

   - Ensure that the interrupt thread follows the effective affinity and
     not the programmed affinity to avoid cross core wakeups.

   - Two new interrupt controller drivers (Microsemi Ocelot and Qualcomm
     PDC)

   - Fix the wakeup path clock handling for Reneasas interrupt chips.

   - Rework the boot time register reset for ARM GIC-V2/3

   - Better suspend/resume support for ARM GIV-V3/ITS

   - Add missing locking to the ARM GIC set_type() callback

   - Small fixes for the irq simulator code

   - SPDX identifiers for the irq core code and removal of boiler plate

   - Small cleanups all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  openrisc: Set CONFIG_MULTI_IRQ_HANDLER
  arm64: Set CONFIG_MULTI_IRQ_HANDLER
  genirq: Make GENERIC_IRQ_MULTI_HANDLER depend on !MULTI_IRQ_HANDLER
  irqchip/gic: Take lock when updating irq type
  irqchip/gic: Update supports_deactivate static key to modern api
  irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
  irqchip: Add a driver for the Microsemi Ocelot controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
  irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
  irqchip/gic-v3: Don't try to reset AP0Rn
  irqchip/gic-v3: Do not check trigger configuration of partitionned LPIs
  genirq: Remove license boilerplate/references
  genirq: Add missing SPDX identifiers
  genirq/matrix: Cleanup SPDX identifier
  genirq: Cleanup top of file comments
  genirq: Pass desc to __irq_free instead of irq number
  irqchip/gic-v3: Loudly complain about the use of IRQ_TYPE_NONE
  irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE
  RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
  genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
  ...
2018-04-04 15:19:26 -07:00