Граф коммитов

4958 Коммитов

Автор SHA1 Сообщение Дата
Gabriel Fernandez e631ad60d2 clk: stm32mp1: add missing static
Add missing static for const parent names and clock ops.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 13:42:43 -07:00
Stephen Boyd b44c4ddf4a Merge branch 'clk-davinci' into clk-next
* clk-davinci:
  clk: davinci: add a reset lookup table for psc0
  reset: modify the way reset lookup works for board files
  reset: add support for non-DT systems
2018-04-06 13:38:08 -07:00
Bartosz Golaszewski 5ced192312 clk: davinci: add a reset lookup table for psc0
In order to be able to use the reset framework in legacy boot mode as
well, add the reset lookup table to the psc driver for da850 variant.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 13:37:19 -07:00
Stephen Boyd a339bdf64a Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and 'clk-imx6sll' into clk-next
* clk-stratix10:
  clk: socfpga: stratix10: add clock driver for Stratix10 platform
  dt-bindings: documentation: add clock bindings information for Stratix10

* clk-imx:
  clk: imx7d: Move clks_init_on before any clock operations
  clk: imx7d: Correct ahb clk parent select
  clk: imx7d: Correct dram pll type
  clk: imx7d: Add USB clock information
  clk: imx: pllv2: avoid using uninitialized values
  clk: imx6ull: Add epdc_podf instead of sim_podf
  clk: imx: imx7d: correct video pll clock tree
  clk: imx: imx7d: add the Keypad Port module clock
  clk: imx7d: add CAAM clock
  clk: imx: imx7d: add the snvs clock
  clk: imx: imx6sx: update cko mux options

* clk-bcm:
  clk: bcm2835: De-assert/assert PLL reset signal when appropriate

* clk-cs2000:
  clk: cs2000: set pm_ops in hibernate-compatible way

* clk-imx6sll:
  clk: imx: add clock driver for imx6sll
  dt-bindings: imx: update clock doc for imx6sll
  clk: imx: add new gate/gate2 wrapper funtion
  clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
2018-04-06 13:22:12 -07:00
Stephen Boyd a83fdfae5a Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and 'clk-ti-flag-fix' into clk-next
* clk-davinci:
  clk: davinci: Remove redundant dev_err calls
  clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
  clk: davinci: New driver for TI DA8XX CFGCHIP clocks
  dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks
  clk: davinci: Add platform information for TI DM646x PSC
  clk: davinci: Add platform information for TI DM644x PSC
  clk: davinci: Add platform information for TI DM365 PSC
  clk: davinci: Add platform information for TI DM355 PSC
  clk: davinci: Add platform information for TI DA850 PSC
  clk: davinci: Add platform information for TI DA830 PSC
  clk: davinci: New driver for davinci PSC clocks
  dt-bindings: clock: New bindings for TI Davinci PSC
  clk: davinci: Add platform information for TI DM646x PLL
  clk: davinci: Add platform information for TI DM644x PLL
  clk: davinci: Add platform information for TI DM365 PLL
  clk: davinci: Add platform information for TI DM355 PLL
  clk: davinci: Add platform information for TI DA850 PLL
  clk: davinci: Add platform information for TI DA830 PLL
  clk: davinci: New driver for davinci PLL clocks
  dt-bindings: clock: Add new bindings for TI Davinci PLL clocks

* clk-si544:
  clk: Add driver for the si544 clock generator chip

* clk-rockchip:
  clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
  clk: rockchip: Fix error return in phase clock registration
  clk: rockchip: Correct the behaviour of restoring cached phase
  clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
  clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
  clk: rockchip: Add 1.6GHz PLL rate for rk3399
  clk: rockchip: Restore the clock phase after the rate was changed
  clk: rockchip: Prevent calculating mmc phase if clock rate is zero
  clk: rockchip: Free the memory on the error path
  clk: rockchip: document hdmi_phy external input for rk3328
  clk: rockchip: add flags for rk3328 dclk_lcdc
  clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
  clk: rockchip: protect all remaining rk3328 interconnect clocks
  clk: rockchip: export sclk_hdmi_sfc on rk3328
  clk: rockchip: remove HCLK_VIO from rk3328 dt header
  clk: rockchip: fix hclk_vio_niu on rk3328

* clk-uniphier:
  clk: uniphier: add additional ethernet clock lines for Pro4
  clk: uniphier: add SATA clock control support
  clk: uniphier: add PCIe clock control support
  clk: uniphier: add ethernet clock control support for PXs3
  clk: uniphier: add Pro4/Pro5/PXs2 audio system clock

* clk-ti-flag-fix:
  clk: ti: fix flag space conflict with clkctrl clocks
  clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
2018-04-06 13:22:06 -07:00
Stephen Boyd b03781920c Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next
* clk-mediatek:
  clk: mediatek: add audsys support for MT2701
  clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
  dt-bindings: clock: mediatek: add audsys support for MT2701
  dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
  clk: mediatek: update missing clock data for MT7622 audsys
  clk: mediatek: fix PWM clock source by adding a fixed-factor clock
  dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4

* clk-hisi:
  clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
  clk: hisilicon: mark wdt_mux_p[] as const
  clk: hisilicon: Mark phase_ops static
  clk: hi3798cv200: add emmc sample and drive clock
  clk: hisilicon: add hisi phase clock support
  clk: hi3798cv200: add COMBPHY0 clock support
  clk: hi3798cv200: fix define indentation
  clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
  clk: hi3798cv200: correct IR clock parent
  clk: hi3798cv200: fix unregister call sequence in error path

* clk-allwinner:
  clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
  clk: sunxi-ng: add support for the Allwinner H6 CCU
  dt-bindings: add device tree binding for Allwinner H6 main CCU
  clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
  clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
  clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
  clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
  clk: sunxi-ng: Add check for minimal rate to NM PLLs
  clk: sunxi-ng: Use u64 for calculation of nkmp rate
  clk: sunxi-ng: Mask nkmp factors when setting register
  clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name

* clk-ux500:
  clk: ux500: Drop AB8540/9540 support

* clk-renesas: (27 commits)
  clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
  clk: renesas: rcar-gen3: Always use readl()/writel()
  clk: renesas: sh73a0: Always use readl()/writel()
  clk: renesas: rza1: Always use readl()/writel()
  clk: renesas: rcar-gen2: Always use readl()/writel()
  clk: renesas: r8a7740: Always use readl()/writel()
  clk: renesas: r8a73a4: Always use readl()/writel()
  clk: renesas: mstp: Always use readl()/writel()
  clk: renesas: div6: Always use readl()/writel()
  clk: fix false-positive Wmaybe-uninitialized warning
  clk: renesas: r8a77965: Replace DU2 clock
  clk: renesas: cpg-mssr: Add support for R-Car M3-N
  clk: renesas: cpg-mssr: add R8A77980 support
  dt-bindings: clock: add R8A77980 CPG core clock definitions
  clk: renesas: r8a7792: Add rwdt clock
  clk: renesas: r8a7794: Add rwdt clock
  clk: renesas: r8a7791/r8a7793: Add rwdt clock
  clk: renesas: r8a7790: Add rwdt clock
  clk: renesas: r8a7745: Add rwdt clock
  clk: renesas: r8a7743: Add rwdt clock
  ...
2018-04-06 13:21:57 -07:00
Stephen Boyd fbc20b8c3c Merge branches 'clk-mvebu', 'clk-phase', 'clk-nxp', 'clk-mtk2712' and 'clk-qcom-rpmcc' into clk-next
* clk-mvebu:
  clk: mvebu: armada-38x: add support for missing clocks
  clk: mvebu: cp110: Fix clock tree representation

* clk-phase:
  clk: Don't show the incorrect clock phase
  clk: update cached phase to respect the fact when setting phase

* clk-nxp:
  clk: lpc32xx: Set name of regmap_config

* clk-mtk2712:
  clk: mediatek: update clock driver of MT2712
  dt-bindings: clock: add clocks for MT2712

* clk-qcom-rpmcc:
  clk: qcom: rpmcc: Add support to XO buffered clocks
2018-04-06 13:21:52 -07:00
Stephen Boyd e8121d9867 Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next
* clk-spreadtrum:
  clk: sprd: add RTC gate for SC9860
  dt-bindings: clocks: add APB RTC gate for SC9860

* clk-stm32f:
  clk: stm32: Add clk entry for SDMMC2 on stm32F769
  clk: stm32: Add DSI clock for STM32F469 Board
  clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

* clk-stm32mp1:
  clk: stm32: add configuration flags for each of the stm32 drivers
  clk: stm32mp1: add Debug clocks
  clk: stm32mp1: add MCO clocks
  clk: stm32mp1: add RTC clock
  clk: stm32mp1: add Peripheral & Kernel Clocks
  clk: stm32mp1: add Kernel timers
  clk: stm32mp1: add Sub System clocks
  clk: stm32mp1: add Post-dividers for PLL
  clk: stm32mp1: add PLL clocks
  clk: stm32mp1: add Source Clocks for PLLs
  clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators
  clk: stm32mp1: Introduce STM32MP1 clock driver
  dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings

* clk-hi655x:
  clk: enable hi655x common clk automatically

* clk-gpio:
  clk: clk-gpio: Allow GPIO to sleep in set/get_parent
2018-04-06 13:21:45 -07:00
Stephen Boyd caa9f3b7d7 Merge branches 'clk-versatile', 'clk-doc', 'clk-must-check', 'clk-qcom' and 'clk-debugfs' into clk-next
* clk-versatile:
  clk: versatile: Remove WARNs in ->round_rate()
  clk: versatile: add min/max rate boundaries for vexpress osc clock

* clk-doc:
  Documentation: clk: enable lock is not held for clk_is_enabled API

* clk-must-check:
  clk: add more __must_check for bulk APIs

* clk-qcom:
  clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider()
  clk: qcom: gcc-msm8996: Mark aggre0 noc clks as critical

* clk-debugfs:
  clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro
2018-04-06 13:21:39 -07:00
Stephen Boyd 15afa044cb Merge branches 'clk-ti', 'clk-amlogic', 'clk-tegra' and 'clk-samsung' into clk-next
* clk-ti:
  clk: keystone: sci-clk: add support for dynamically probing clocks
  clk: ti: add support for clock latching to mux clocks
  clk: ti: add support for clock latching to divider clocks
  clk: ti: add generic support for clock latching
  clk: ti: add support for register read-modify-write low-level operation
  dt-bindings: clock: ti: add latching support to mux and divider clocks

* clk-amlogic: (50 commits)
  clk: meson: Drop unused local variable and add static
  clk: meson: clean-up clk81 clocks
  clk: meson: add fdiv clock gates
  clk: meson: add mpll pre-divider
  clk: meson: axg: add hifi pll clock
  clk: meson: axg: add hifi clock bindings
  clk: meson: add ROUND_CLOSEST to the pll driver
  clk: meson: add gp0 frac parameter for axg and gxl
  clk: meson: improve pll driver results with frac
  clk: meson: remove special gp0 lock loop
  clk: meson: poke pll CNTL last
  clk: meson: add fractional part of meson8b fixed_pll
  clk: meson: use hhi syscon if available
  clk: meson: remove obsolete cpu_clk
  clk: meson: rework meson8b cpu clock
  clk: meson: split divider and gate part of mpll
  clk: meson: migrate plls clocks to clk_regmap
  clk: meson: migrate the audio divider clock to clk_regmap
  clk: meson: migrate mplls clocks to clk_regmap
  clk: meson: add regmap helpers for parm
  ...

* clk-tegra:
  clk: tegra: Fix pll_u rate configuration
  clk: tegra: Specify VDE clock rate
  clk: tegra20: Correct PLL_C_OUT1 setup
  clk: tegra: Mark HCLK, SCLK and EMC as critical
  clk: tegra: MBIST work around for Tegra210
  clk: tegra: add fence_delay for clock registers
  clk: tegra: Add la clock for Tegra210

* clk-samsung: (22 commits)
  clk: samsung: Mark a few things static
  clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
  clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
  clk: samsung: exynos5420: Add more entries to EPLL rate table
  clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
  clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
  clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
  clk: samsung: Add Exynos5 sub-CMU clock driver
  soc: samsung: pm_domains: Add blacklisting clock handling
  clk: samsung: Add compile time PLL rate validators
  clk: samsung: s3c2410: Fix PLL rates
  clk: samsung: exynos7: Fix PLL rates
  clk: samsung: exynos5433: Fix PLL rates
  clk: samsung: exynos5260: Fix PLL rates
  clk: samsung: exynos5250: Fix PLL rates
  clk: samsung: exynos3250: Fix PLL rates
  clk: exynos5433: Extend list of available AUD_PLL output frequencies
  clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk
  clk: samsung: Add a git tree entry to MAINTAINERS
  clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe()
  ...
2018-04-06 13:21:33 -07:00
Bai Ping 4a5f720b65 clk: imx: add clock driver for imx6sll
Add clk driver support for imx6sll.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 11:27:27 -07:00
Bai Ping 2b18cc1f12 clk: imx: add new gate/gate2 wrapper funtion
Add new gate/gate2 wrapper function to register clocks with optional flags.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 11:27:25 -07:00
Bai Ping 6f9575e556 clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
The busy divider and busy mux is actually used by the system critical clocks,
so add 'CLK_IS_CRITICAL' to clocks registered with these two type.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 11:27:24 -07:00
Nikita Yushchenko eade4ccdb0 clk: cs2000: set pm_ops in hibernate-compatible way
Use SET_LATE_SYSTEM_SLEEP_PM_OPS() macro instead of direct assignment to
.resume_early field.

This fixes initialization of CS2000 in restore from hibernation in case
of kernel used to load image did not initialize CS2000 while kernel
being restored had CS2000 initialized.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 11:22:44 -07:00
Boris Brezillon 753872373b clk: bcm2835: De-assert/assert PLL reset signal when appropriate
In order to enable a PLL, not only the PLL has to be powered up and
locked, but you also have to de-assert the reset signal. The last part
was missing. Add it so PLLs that were not enabled by the FW/bootloader
can be enabled from Linux.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 11:15:42 -07:00
Dong Aisheng 8d41e6538c clk: imx7d: Move clks_init_on before any clock operations
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.

Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:14:04 -07:00
Anson Huang a12ec8b653 clk: imx7d: Correct ahb clk parent select
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:14:03 -07:00
Anson Huang afe7c08a03 clk: imx7d: Correct dram pll type
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.

There is a test_div placed before DRAM PLL's gate, so
add this test div clk.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:13:59 -07:00
Peter Chen 5fcb4c76bb clk: imx7d: Add USB clock information
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:13:55 -07:00
Dinh Nguyen 07afb8db73 clk: socfpga: stratix10: add clock driver for Stratix10 platform
Add a clock driver for the Stratix10 SoC. The driver is similar to the
Cyclone5/Arria10 platforms, with the exception that this driver only uses
one single clock binding.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:12:35 -07:00
Linus Torvalds 38c23685b2 ARM: SoC driver updates for 4.17
The main addition this time around is the new ARM "SCMI" framework,
 which is the latest in a series of standards coming from ARM to do power
 management in a platform independent way. This has been through many
 review cycles, and it relies on a rather interesting way of using the
 mailbox subsystem, but in the end I agreed that Sudeep's version was
 the best we could do after all.
 
 Other changes include:
 
 - the ARM CCN driver is moved out of drivers/bus into drivers/perf,
   which makes more sense. Similarly, the performance monitoring
   portion of the CCI driver are moved the same way and cleaned up
   a little more.
 
 - a series of updates to the SCPI framework
 
 - support for the Mediatek mt7623a SoC in drivers/soc
 
 - support for additional NVIDIA Tegra hardware in drivers/soc
 
 - a new reset driver for Socionext Uniphier
 
 - lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
   drivers/firmware and drivers/reset across platforms
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "The main addition this time around is the new ARM "SCMI" framework,
  which is the latest in a series of standards coming from ARM to do
  power management in a platform independent way.

  This has been through many review cycles, and it relies on a rather
  interesting way of using the mailbox subsystem, but in the end I
  agreed that Sudeep's version was the best we could do after all.

  Other changes include:

   - the ARM CCN driver is moved out of drivers/bus into drivers/perf,
     which makes more sense. Similarly, the performance monitoring
     portion of the CCI driver are moved the same way and cleaned up a
     little more.

   - a series of updates to the SCPI framework

   - support for the Mediatek mt7623a SoC in drivers/soc

   - support for additional NVIDIA Tegra hardware in drivers/soc

   - a new reset driver for Socionext Uniphier

   - lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
     drivers/firmware and drivers/reset across platforms"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
  reset: uniphier: add ethernet reset control support for PXs3
  reset: stm32mp1: Enable stm32mp1 reset driver
  dt-bindings: reset: add STM32MP1 resets
  reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control
  reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
  reset: modify the way reset lookup works for board files
  reset: add support for non-DT systems
  clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
  firmware: arm_scmi: prevent accessing rate_discrete uninitialized
  hwmon: (scmi) return -EINVAL when sensor information is unavailable
  amlogic: meson-gx-socinfo: Update soc ids
  soc/tegra: pmc: Use the new reset APIs to manage reset controllers
  soc: mediatek: update power domain data of MT2712
  dt-bindings: soc: update MT2712 power dt-bindings
  cpufreq: scmi: add thermal dependency
  soc: mediatek: fix the mistaken pointer accessed when subdomains are added
  soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
  soc: mediatek: avoid hardcoded value with bus_prot_mask
  dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
  dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC
  ...
2018-04-05 21:29:35 -07:00
Linus Torvalds b240b419db ARM: SoC device tree updates for 4.17
This is the usual set of changes for device trees, with over 700
 non-merged changesets. There is an ongoing set of dtc warning fixes and
 the usual bugfixes, cleanups and added device support.
 
 The most interesting bit as usual is support for new machines listed
 below:
 
 - The Allwinner H6 makes its debut with the Pine-H64 board, and we get
   two new machines based on its older siblings: the H5 based OrangePi
   Zero+ and the A64 based Teres-I Laptop from Olimex. On the 32-bit side,
   we add The Olimex som204 based on Allwinner A20, and the Banana Pi M2
   Zero development board (based on H2).
 
 - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972
   development board and p2888 CPU module.
 
 - The Nuvoton npcm750 is a BMC that was newly added, for now we only
   support running on the evaluation board.
 
 - STmicroelectronics stm32 gains support for the stm32mp157c and two
   evaluation boards.
 
 - The Toradex Colibri board family grows a few members based on the
   i.MX6ULL variant.
 
 - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6
   family of chips.
 
 - The Phytec phyBOARD Mira is a family of industrial boards based on
   i.MX6. For now, four models get added.
 
 - TI am335x based PDU-001 is an industrial embedded machine used for
   traffic monitoring
 
 - The Aspeed platform now supports running on the BMC on the Qualcomm
   Centriq 2400 server
 
 - Samsung Exynos4 based Galaxy S3 is a family of mobile phones Qualcomm
   msm8974 based Galaxy S5 is a rather different phone made by the same
   company.
 
 - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file
   for the various boards made by Xilinx themselves, as well as the
   Digilent Zybo Z7.
 
 - The ARM Versatile family now supports the "IB2" interface board.
 
 - The Renesas H2 based "Stout" and the H3 based Salvator-X are more
   evaluation boards named after a kind of beer, as most of them are.
   The r8a77980 (V3H) based "Condor" apparently doesn't follow that
   tradition. ;-)
 
 - ROC-RK3328-CC is a simple developement board from the Libre Computer
   Project, based on the Rockchips RK3328 SoC
 
 - Haiku is another development board plus Qseven module based on Rockchips
   RK3368 and made by Theobroma Systems.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates from Arnd Bergmann:
 "This is the usual set of changes for device trees, with over 700
  non-merged changesets. There is an ongoing set of dtc warning fixes
  and the usual bugfixes, cleanups and added device support.

  The most interesting bit as usual is support for new machines listed
  below:

   - The Allwinner H6 makes its debut with the Pine-H64 board, and we
     get two new machines based on its older siblings: the H5 based
     OrangePi Zero+ and the A64 based Teres-I Laptop from Olimex. On the
     32-bit side, we add The Olimex som204 based on Allwinner A20, and
     the Banana Pi M2 Zero development board (based on H2).

   - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972
     development board and p2888 CPU module.

   - The Nuvoton npcm750 is a BMC that was newly added, for now we only
     support running on the evaluation board.

   - STmicroelectronics stm32 gains support for the stm32mp157c and two
     evaluation boards.

   - The Toradex Colibri board family grows a few members based on the
     i.MX6ULL variant.

   - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6 family
     of chips.

   - The Phytec phyBOARD Mira is a family of industrial boards based on
     i.MX6. For now, four models get added.

   - TI am335x based PDU-001 is an industrial embedded machine used for
     traffic monitoring

   - The Aspeed platform now supports running on the BMC on the Qualcomm
     Centriq 2400 server

   - Samsung Exynos4 based Galaxy S3 is a family of mobile phones
     Qualcomm msm8974 based Galaxy S5 is a rather different phone made
     by the same company.

   - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file
     for the various boards made by Xilinx themselves, as well as the
     Digilent Zybo Z7.

   - The ARM Versatile family now supports the "IB2" interface board.

   - The Renesas H2 based "Stout" and the H3 based Salvator-X are more
     evaluation boards named after a kind of beer, as most of them are.
     The r8a77980 (V3H) based "Condor" apparently doesn't follow that
     tradition. ;-)

   - ROC-RK3328-CC is a simple developement board from the Libre
     Computer Project, based on the Rockchips RK3328 SoC

   - Haiku is another development board plus Qseven module based on
     Rockchips RK3368 and made by Theobroma Systems"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (701 commits)
  arm: dts: modify Nuvoton NPCM7xx device tree structure
  arm: dts: modify Makefile NPCM750 configuration name
  arm: dts: modify clock binding in NPCM750 device tree
  arm: dts: modify timer register size in NPCM750 device tree
  arm: dts: modify UART compatible name in NPCM750 device tree
  arm: dts: add watchdog device to NPCM750 device tree
  arm64: dts: uniphier: add ethernet node for PXs3
  ARM: dts: uniphier: add pinctrl groups of ethernet for second instance
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for board using GPL-2.0+
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0+/MIT
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0
  arm: dts: armada-385-turris-omnia: use SPDX-License-Identifier
  arm: dts: armada-385-db-ap: use SPDX-License-Identifier
  arm: dts: armada-388-rd: use SPDX-License-Identifier
  arm: dts: armada-xp-db-xc3-24g4xg: use SPDX-License-Identifier
  arm: dts: armada-xp-db-dxbc2: use SPDX-License-Identifier
  arm: dts: armada-370-db: use SPDX-License-Identifier
  arm: dts: armada-*.dts: use SPDX-License-Identifier for most of the Armada based board
  arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs
  arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs
  ...
2018-04-05 21:18:09 -07:00
Tero Kristo 269bd202bc clk: ti: fix flag space conflict with clkctrl clocks
The introduction of support for CLK_SET_RATE_PARENT flag for clkctrl
clocks used a generic clock flag, which causes a conflict with the
rest of the clkctrl flags, namely the NO_IDLEST flag. This can cause
boot failures on certain platforms where this flag is introduced, by
omitting the wait for the clockctrl module to be fully enabled before
proceeding with rest of the code.

Fix this by moving all the clkctrl specific flags to their own bit-range.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Fixes: 49159a9dc3 ("clk: ti: add support for CLK_SET_RATE_PARENT flag")
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Tested-by: Tony Lindgren <tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-05 15:25:22 -07:00
Kunihiko Hayashi 6f1aa4ef3f clk: uniphier: add additional ethernet clock lines for Pro4
Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-05 15:03:51 -07:00
Kunihiko Hayashi 54e1f7ee1f clk: uniphier: add SATA clock control support
Add clock control for SATA controller on UniPhier SoCs. This adds
support for PXs2, LD20 and PXs3.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-05 15:03:49 -07:00
Kunihiko Hayashi 2e277efb82 clk: uniphier: add PCIe clock control support
Add clock control for PCIe controller on UniPhier SoCs. This adds
support for Pro5, LD20 and PXs3.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-05 15:03:45 -07:00
Mike Looijmans 953cc3e811 clk: Add driver for the si544 clock generator chip
This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-23 10:05:25 -07:00
Wei Yongjun fc3fcb4ff1 clk: davinci: Remove redundant dev_err calls
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-23 09:44:45 -07:00
Stephen Boyd aa584d28f3 clk: renesas: Updates for v4.17 (take two)
- Fix the incorrect display clock on R-Car M3-N,
   - Always use readl()/writel(),
   - Small fixes.
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Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Fix the incorrect display clock on R-Car M3-N,
  - Always use readl()/writel(),
  - Small fixes.

* tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
  clk: renesas: rcar-gen3: Always use readl()/writel()
  clk: renesas: sh73a0: Always use readl()/writel()
  clk: renesas: rza1: Always use readl()/writel()
  clk: renesas: rcar-gen2: Always use readl()/writel()
  clk: renesas: r8a7740: Always use readl()/writel()
  clk: renesas: r8a73a4: Always use readl()/writel()
  clk: renesas: mstp: Always use readl()/writel()
  clk: renesas: div6: Always use readl()/writel()
  clk: renesas: r8a77965: Replace DU2 clock
2018-03-23 09:40:52 -07:00
Kunihiko Hayashi c2fd8756c5 clk: uniphier: add ethernet clock control support for PXs3
Add clock control for ethernet controller on PXs3 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-23 09:39:36 -07:00
Linus Walleij 726fef09b8 clk: ux500: Drop AB8540/9540 support
The AB8540 was an evolved version of the AB8500, but it was never
mass produced or put into products, only reference designs exist.
The upstream support was never completed and it is unlikely that
this will happen so drop the support for now to simplify
maintenance of the AB8500.

Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-23 09:36:11 -07:00
Lin Huang 9dc486fdf6 clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23 09:09:19 +01:00
Shawn Lin 0d92d1802c clk: rockchip: Fix error return in phase clock registration
The newly added clock notifier may return an error code but so far the
error output in the function would only return an error pointer from
registering the clock.

So when the clock notifier fails the clock would be unregistered but the
return would still be the clock pointer which could then not be
dereferenced correctly. So fix the error handling to prevent that.

Fixes: 60cf09e45f ("clk: rockchip: Restore the clock phase after the rate was changed")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23 09:08:43 +01:00
Shawn Lin 570fda972b clk: rockchip: Correct the behaviour of restoring cached phase
We can't restore every phase, for instance the invalid phase and
the phase for coming rate which is out of the scope of boards'
ability. And this patch also corrects the error path to return
invalid pointer to clk if clk_notifier_register failed introduced
by the same offending commit.

Fixes: 60cf09e45f ("clk: rockchip: Restore the clock phase after the rate was changed")
Reported-by: wlq <wlq@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: wlq <wlq@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23 09:02:58 +01:00
Shawn Lin ce84eca927 clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23 08:58:19 +01:00
Shawn Lin 4b0556a441 clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23 08:49:35 +01:00
Magnus Damm 472f5f3918 clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
Adjust the R8A77980-specific #ifdefs to use CLK instead of ARCH
to follow same style as other SoCs.

Fixes: ce15783c51 ("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 17:35:02 +01:00
Geert Uytterhoeven 2b935d524d clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().

Cfr. commit 30ad3cf00e ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:35:00 +01:00
Geert Uytterhoeven f046d6a6bf clk: renesas: sh73a0: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:58 +01:00
Geert Uytterhoeven fcf371b351 clk: renesas: rza1: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:57 +01:00
Geert Uytterhoeven 6c669e504a clk: renesas: rcar-gen2: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:54 +01:00
Geert Uytterhoeven f32b0696ea clk: renesas: r8a7740: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:53 +01:00
Geert Uytterhoeven b86b493eb2 clk: renesas: r8a73a4: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:51 +01:00
Geert Uytterhoeven 8027519840 clk: renesas: mstp: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:49 +01:00
Geert Uytterhoeven c733c7d937 clk: renesas: div6: Always use readl()/writel()
On arm32/arm64, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel().  Hence use the generic readl()/writel()
instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 17:34:29 +01:00
Icenowy Zheng f422fa558a
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing
in the ccu-sun50i-h6 driver.

Add this missing clock to the driver.

Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-21 12:27:13 +01:00
Wei Yongjun c744b63b6c clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.

This is detected by Coccinelle semantic patch.

@@
expression pdev, res, n, t, e, e1, e2;
@@

res = platform_get_resource(pdev, t, n);
+ if (!res)
+   return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Fixes: 322269163a ("clk: hisilicon: add hisi_clk_alloc function.")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:23:41 -07:00
David Lechner 58e1e2d2cd clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon
register on TI DA8XX-type SoCs.

The USB0 (USB 2.0) PHY clock is an interesting case because it calls
clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled
temporarily while we are locking the PLL, which takes place during the
clk_enable() callback.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 1e88a8d64f clk: davinci: New driver for TI DA8XX CFGCHIP clocks
This adds a new driver for the gate and multiplexer clocks in the
CFGCHIPn syscon registers on TI DA8XX-type SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner aad739f946 clk: davinci: Add platform information for TI DM646x PSC
This adds platform-specific declarations for the PSC clocks on TI
DM646x based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner f41e527575 clk: davinci: Add platform information for TI DM644x PSC
This adds platform-specific declarations for the PSC clocks on TI
DM644x based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 9ab1102cce clk: davinci: Add platform information for TI DM365 PSC
This adds platform-specific declarations for the PSC clocks on TI
DM365 based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner b99bfca56e clk: davinci: Add platform information for TI DM355 PSC
This adds platform-specific declarations for the PSC clocks on TI
DM355 based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner a47d604062 clk: davinci: Add platform information for TI DA850 PSC
This adds platform-specific declarations for the PSC clocks on TI DA850/
OMAP-L138/AM18XX SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner c2952e271b clk: davinci: Add platform information for TI DA830 PSC
This adds platform-specific declarations for the PSC clocks on TI DA830/
OMAP-L137/AM17XX SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner c6ed4d734b clk: davinci: New driver for davinci PSC clocks
This adds a new driver for mach-davinci PSC clocks. This is porting the
code from arch/arm/mach-davinci/psc.c to the common clock framework and
is converting it to use regmap to simplify the code. Additionally, it
adds device tree support for these clocks.

Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the keystone
driver makes the assumption that there is only one PSC per SoC and uses
global variables, but here we have two controllers per SoC.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 6ef35851a0 clk: davinci: Add platform information for TI DM646x PLL
This adds platform-specific declarations for the PLL clocks on TI
DM646x based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner d67c13eaf7 clk: davinci: Add platform information for TI DM644x PLL
This adds platform-specific declarations for the PLL clocks on TI
DM644x based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 650bba61fc clk: davinci: Add platform information for TI DM365 PLL
This adds platform-specific declarations for the PLL clocks on TI
DM365 based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner dcdd19b269 clk: davinci: Add platform information for TI DM355 PLL
This adds platform-specific declarations for the PLL clocks on TI
DM355 based systems.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 55b3caed2b clk: davinci: Add platform information for TI DA850 PLL
This adds platform-specific declarations for the PLL clocks on TI DA850/
OMAP-L138/AM18XX SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner c92765fdb8 clk: davinci: Add platform information for TI DA830 PLL
This adds platform-specific declarations for the PLL clocks on TI DA830/
OMAP-L137/AM17XX SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
David Lechner 2d17269151 clk: davinci: New driver for davinci PLL clocks
This adds a new driver for mach-davinci PLL clocks. This is porting the
code from arch/arm/mach-davinci/clock.c to the common clock framework.
Additionally, it adds device tree support for these clocks.

The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent
compile errors until the clock code in arch/arm/mach-davinci is removed.

Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the register
layouts are a bit different, which would add even more if/else mess
to the keystone clocks. And the keystone PLL driver doesn't support
setting clock rates.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 10:16:26 -07:00
Sudeep Holla 7f9badfcef clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
Commit aa795c41d9 ("clk: Add devm_of_clk_add_hw_provider()/del_provider()
APIs") adds devm_of_clk_add_hw_provider which takes care of deleting the
clock provider when the clock providers device is removed.

This patch makes use of devm_of_clk_add_hw_provider() instead of
of_clk_add_hw_provider() so that we can eliminate the need of explicit
scmi_clocks_remove for just doing of_clk_del_provider()

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2018-03-20 16:23:26 +00:00
Ryder Lee b572f6393e clk: mediatek: add audsys support for MT2701
Add clock driver support for MT2701 audsys.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 00:24:42 -07:00
Ryder Lee 037b21133e clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
Add devm_of_platform_populate() to populate devices which are children
of the root node.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 00:24:33 -07:00
Amit Nischal 687d7a0caa clk: qcom: Add support for controlling Fabia PLL
Fabia PLL is a Digital Frequency Locked Loop (DFLL) clock
generator which has a wide range of frequency output. It
supports dynamic updating of the output frequency
("frequency slewing") without need to turn off the PLL
before configuration. Add support for initial configuration
and programming sequence to control fabia PLLs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
[sboyd: Shorten code a little]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 16:32:36 -07:00
Amit Nischal bdc3bbdd40 clk: qcom: Clear hardware clock control bit of RCG
For upcoming targets like sdm845, POR value of the hardware clock control
bit is set for most of root clocks which needs to be cleared for software
to be able to control. For older targets like MSM8996, this bit is reserved
bit and having POR value as 0 so this patch will work for the older targets
too. So update the configuration mask to take care of the same to clear
hardware clock control bit.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 15:55:38 -07:00
Srinivas Kandagatla 8bcde6582c clk: qcom: rpmcc: Add support to XO buffered clocks
XO is onchip buffer clock to generate 19.2MHz.

This patch adds support to 5 XO buffer clocks found on PMIC8921,
these buffer clocks can be controlled from external pin or in
manual mode.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 14:40:26 -07:00
Weiyi Lu f72595cf44 clk: mediatek: update clock driver of MT2712
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 14:37:40 -07:00
Jeffy Chen cef7b18c3e clk: lpc32xx: Set name of regmap_config
We are now allowing to register debugfs without a valid device, and not
having a valid name will end up using "dummy*" to create debugfs dir.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 14:35:16 -07:00
Shawn Lin 1f9c63e8de clk: Don't show the incorrect clock phase
It's found that the clock phase output from clk_summary is
wrong compared to the actual phase reading from the register.

cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample     0        1        0 50000000          0 -22

It exposes an issue that clk core, clk_core_get_phase, always
returns the cached core->phase which should be either updated
by calling clk_set_phase or directly from the first place the
clk was registered.

When registering the clk, the core->phase geting from ->get_phase()
may return negative value indicating error. This is quite common
since the clk's phase may be highly related to its parent chain,
but it was temporarily orphan when registered, since its parent
chains hadn't be ready at that time, so the clk drivers decide to
return error in this case. However, if no clk_set_phase is called or
maybe the ->set_phase() isn't even implemented, the core->phase would
never be updated. This is wrong, and we should try to update it when
all its parent chains are settled down, like the way of updating clock
rate for that. But it's not deserved to complicate the code now and
just update it anyway when calling clk_core_get_phase, which would be
much simple and enough.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 14:02:49 -07:00
Richard Genoud 6a4a459580 clk: mvebu: armada-38x: add support for missing clocks
Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
or 1333MHz (industrial).

They have also some dip-switches to select a different clock (666, 800,
1066, 1200).

The funny thing is that the recovery button is on the MPP34 fq selector.
So, when booting an industrial board with this button down, the frequency
666MHz is selected (and the kernel didn't boot).

This patch add all the missing clocks.

The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).

Fixes: 0e85aeced4 ("clk: mvebu: add clock support for Armada 380/385")
Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
Cc: <stable@vger.kernel.org> # 3.16.x

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:53:57 -07:00
Mike Looijmans 2e838e7f3a clk: clk-gpio: Allow GPIO to sleep in set/get_parent
When changing or retrieving clock parents, the caller is in a sleepable
state (like prepare) so the GPIO operation need not be atomic. Replace
gpiod_{g|s}et_value with gpiod_{g|s}et_value_cansleep in the {g|s}et_parent
calls for the GPIO based clock mux.

This fixes a "slowpath" warning when the GPIO controller is an I2C expander
or something similar.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:53:08 -07:00
Riku Voipio 3a49afb84c clk: enable hi655x common clk automatically
Without COMMON_CLK_HI655X Wifi and bluetooth are non-functional on Hikey.
As suggested by Arnd, enable the driver automatically when the parent
driver is selected. With sensible defaults in place, we can leave other
choices for EXPERT.

Cc: John Stultz <john.stultz@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Suggested-by: Arnd Bergmann <arnd@linaro.org>
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:52:20 -07:00
Benjamin Gaignard da32d3539f clk: stm32: add configuration flags for each of the stm32 drivers
Add two configuration flags to be able to not compile all the time
stm32f and stm32h7 drivers when ARCH_STM32 is set.
That help to save some space on those small platforms.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:49:36 -07:00
Patrice Chotard f9acf1057d clk: stm32: Add clk entry for SDMMC2 on stm32F769
STM32F769 has 2 SDMMC port, add clock entry for the second one.

Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:46:07 -07:00
Gabriel Fernandez 2f05b6b920 clk: stm32: Add DSI clock for STM32F469 Board
This patch adds DSI clock for STM32F469 board

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:45:11 -07:00
Katsuhiro Suzuki afeb079bc8 clk: uniphier: add Pro4/Pro5/PXs2 audio system clock
Add clock for audio subsystem (AIO) on UniPhier
Pro4/Pro5/PXs2 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:42:49 -07:00
Ryder Lee 936ceb12c5 clk: mediatek: update missing clock data for MT7622 audsys
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:40:57 -07:00
Sean Wang 89cd7aec21 clk: mediatek: fix PWM clock source by adding a fixed-factor clock
The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.

Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.

Cc: stable@vger.kernel.org
Fixes: e986211827 ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:25:30 -07:00
Gregory CLEMENT c7e92def1e clk: mvebu: cp110: Fix clock tree representation
Thanks to new documentation, we have a better view of the clock tree.
There were few mistakes in the first version of this driver, the main one
being the parental link between the clocks. Actually the tree is more
flat that we though. Most of the IP blocks require two clocks: one for
the IP itself and one for accessing the registers, and unlike what we
wrote there is no link between these two clocks.

The other mistakes were about the name of the clocks: the root clock is
not the Audio PLL but the PLL0, and what we called the EIP clock is named
the x2 Core clock and is used by other IP block than the EIP ones.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 13:10:50 -07:00
Andy Shevchenko fec0ef3f52 clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro
...instead of open coding file operations followed by custom ->open()
callbacks per each attribute.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 10:50:52 -07:00
Boris Brezillon 7997f3b2df clk: bcm2835: Protect sections updating shared registers
CM_PLLx and A2W_XOSC_CTRL registers are accessed by different clock
handlers and must be accessed with ->regs_lock held.
Update the sections where this protection is missing.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 09:27:37 -07:00
Boris Brezillon 49012d1bf5 clk: bcm2835: Fix ana->maskX definitions
ana->maskX values are already '~'-ed in bcm2835_pll_set_rate(). Remove
the '~' in the definition to fix ANA setup.

Note that this commit fixes a long standing bug preventing one from
using an HDMI display if it's plugged after the FW has booted Linux.
This is because PLLH is used by the HDMI encoder to generate the pixel
clock.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19 09:27:23 -07:00
Icenowy Zheng 524353ea48
clk: sunxi-ng: add support for the Allwinner H6 CCU
The Allwinner H6 SoC has a CCU which has been largely rearranged.

Add support for it in the sunxi-ng CCU framework.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-18 21:17:07 +01:00
Icenowy Zheng a910f251ee
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.

Add fixed post divider support to the NKMP style clocks.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-18 21:16:54 +01:00
Fabio Estevam ab525dcccf clk: Print the clock name and warning cause
When getting the clock related warnings, it is useful to know what
is the clock name that is causing the problem and the cause of the
problem.

Add the clock name and the the warning cause to the log, so that the
output becomes clearer like this:

[    2.383969] ------------[ cut here ]------------
[    2.388720] WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:814 clk_core_disable+0xd4/0xf8
[    2.396658] uart4_ipg_gate already disabled

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 16:29:01 -07:00
Arnd Bergmann df934cbcbf clk: hisilicon: mark wdt_mux_p[] as const
The symbol is in the __initconst section but not marked init, which
caused a warning when building with LTO.

This makes it 'const' as was obviously intended.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: c80dfd9bf5 ("clk: hisilicon: add CRG driver for Hi3516CV300 SoC")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:57:53 -07:00
Arnd Bergmann ce33f28493 clk: fix false-positive Wmaybe-uninitialized warning
When we build this driver with on x86-32, gcc produces a false-positive warning:

drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
   return clk_register_fixed_factor(NULL, name, parent_name, 0,

We can work around that warning by adding a fake initialization, I tried
and failed to come up with any better workaround. This is currently one
of few remaining warnings for a 4.14.y randconfig build, so it would be
good to also have it backported at least to that version. Older versions
have more randconfig warnings, so we might not care.

I had not noticed this earlier, because one patch in my randconfig test
tree removes the '-ffreestanding' option on x86-32, and that avoids
the warning. The -ffreestanding flag was originally global but moved
into arch/i386 by Andi Kleen in commit 6edfba1b33 ("[PATCH] x86_64:
Don't define string functions to builtin") as a 'temporary workaround'.

Like many temporary hacks, this turned out to be rather long-lived, from
all I can tell we still need a simple fix to asm/string_32.h before it
can be removed, but I'm not sure about how to best do that.

Cc: stable@vger.kernel.org
Cc: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:54:31 -07:00
Chunyan Zhang b3316a672b clk: sprd: add RTC gate for SC9860
Add a few gate clocks which are used for gating RTC for some
devices on AON area of SC9860.

This patch has been tested on SC9860, with this patch and proper DT
configurations, the watchdog can be initialized and work well.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:53:30 -07:00
Stephen Boyd 91927ff644 clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider()
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:52:39 -07:00
Lucas Stach 93abad369a clk: imx: pllv2: avoid using uninitialized values
Forward the errors returned by __clk_pllv2_set_rate() in the recalc rate
function, to avoid using uninitialized values for the rate calculation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:40:41 -07:00
Srinivas Kandagatla 496037c015 clk: qcom: gcc-msm8996: Mark aggre0 noc clks as critical
aggre0 bus clks are not associated with any of the drivers, so its
important that these clks are always on to get peripherals on this
bus working. So mark them as critical.

Eventually when we have a proper bus driver these clks can be marked
appropriately.

Without this patch pcie on db820c is not functional.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:35:35 -07:00
Brian Starkey a1d803d78b clk: versatile: Remove WARNs in ->round_rate()
clk_round_rate() is intended to be used to round a given clock rate to
the closest one achievable by the actual clock. This implies that the
input to clk_round_rate() is expected to be unachievable - and such
cases shouldn't be treated as exceptional.

To reflect this, remove the WARN_ONs which trigger when an unachievable
clock rate is passed to vexpress_osc_round_rate().

Reported-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:31:16 -07:00
Sudeep Holla aff2dc6b49 clk: versatile: add min/max rate boundaries for vexpress osc clock
Clock framework has a provider API(clk_hw_set_rate_range) to set the
min/max rate of a clock. Use the same to set the boundaries for the
vexpress osc clock.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 15:29:54 -07:00
Stephen Boyd 1871f0fcba clk: samsung: Mark a few things static
Running sparse on the samsung clk directory has some noise that we can
fix to look for future problems easier.

drivers/clk/samsung/clk-s3c2443.c:111:26: warning: symbol 's3c2443_common_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:139:26: warning: symbol 's3c2443_common_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:152:27: warning: symbol 's3c2443_common_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:186:28: warning: symbol 's3c2443_common_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:241:26: warning: symbol 's3c2416_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:247:26: warning: symbol 's3c2416_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:253:27: warning: symbol 's3c2416_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:263:28: warning: symbol 's3c2416_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:291:26: warning: symbol 's3c2443_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:296:27: warning: symbol 's3c2443_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:305:28: warning: symbol 's3c2443_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:321:26: warning: symbol 's3c2450_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:328:26: warning: symbol 's3c2450_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:334:27: warning: symbol 's3c2450_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:345:28: warning: symbol 's3c2450_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:368:33: warning: symbol 's3c2443_common_frate_clks' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2443.c:464:49: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2443.c:470:49: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2443.c:476:49: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2412.c:96:26: warning: symbol 's3c2412_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:108:35: warning: symbol 's3c2412_ffactor' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:128:26: warning: symbol 's3c2412_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:146:27: warning: symbol 's3c2412_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:177:28: warning: symbol 's3c2412_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:227:33: warning: symbol 's3c2412_common_frate_clks' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2412.c:292:43: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2410.c:98:26: warning: symbol 's3c2410_common_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:114:26: warning: symbol 's3c2410_common_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:119:27: warning: symbol 's3c2410_common_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:138:28: warning: symbol 's3c2410_common_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:203:26: warning: symbol 's3c2410_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:207:35: warning: symbol 's3c2410_ffactor' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:218:28: warning: symbol 's3c2410_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:272:26: warning: symbol 's3c244x_common_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:277:35: warning: symbol 's3c244x_common_ffactor' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:294:26: warning: symbol 's3c244x_common_dividers' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:302:27: warning: symbol 's3c244x_common_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:306:28: warning: symbol 's3c244x_common_aliases' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:321:26: warning: symbol 's3c2440_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:325:27: warning: symbol 's3c2440_gates' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:331:35: warning: symbol 's3c2442_ffactor' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:337:26: warning: symbol 's3c2442_muxes' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:346:33: warning: symbol 's3c2410_common_frate_clks' was not declared. Should it be static?
drivers/clk/samsung/clk-s3c2410.c:471:49: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2410.c:477:49: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-s3c2410.c:483:49: warning: Using plain integer as NULL pointer

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-16 09:23:17 -07:00
Sylwester Nawrocki 182c084da5 clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
This additional frequency is required for HDMI audio support
on Odroid U3 board.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-15 19:27:29 +01:00
Eddie James 8a53fc511c clk: aspeed: Prevent reset if clock is enabled
According to the Aspeed specification, the reset and enable sequence
should be done when the clock is stopped. The specification doesn't
define behavior if the reset is done while the clock is enabled.

From testing on the AST2500, the LPC Controller has problems if the
clock is reset while enabled.

Therefore, check whether the clock is enabled or not before performing
the reset and enable sequence in the Aspeed clock driver.

Reported-by: Lei Yu <mine260309@gmail.com>
Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Fixes: 15ed8ce5f8 ("clk: aspeed: Register gated clocks")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-15 11:13:49 -07:00
Eddie James d90c76bb61 clk: aspeed: Fix is_enabled for certain clocks
Some of the Aspeed clocks are disabled by setting the relevant bit in
the "clock stop control" register to one, while others are disabled by
setting their bit to zero. The driver already uses a flag per gate  to
identify this behavior, but doesn't apply it in the clock is_enabled
function.

Use the existing gate flag to correctly return whether or not a clock
is enabled in the aspeed_clk_is_enabled function.

Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Fixes: 6671507f0f ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-15 11:11:43 -07:00
Stephen Boyd 5d1c04dde0 clk: meson: Drop unused local variable and add static
Fixes the following warnings:

drivers/clk/meson/meson8b.c:512:19: warning: symbol 'meson8b_mpeg_clk_div' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:526:19: warning: symbol 'meson8b_clk81' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:540:19: warning: symbol 'meson8b_cpu_in_sel' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:591:19: warning: symbol 'meson8b_cpu_scale_div' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:608:19: warning: symbol 'meson8b_cpu_scale_out_sel' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:626:19: warning: symbol 'meson8b_cpu_clk' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:392:27: warning: symbol 'gxbb_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:439:27: warning: symbol 'gxl_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/axg.c:195:27: warning: symbol 'axg_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/axg.c:248:27: warning: symbol 'axg_hifi_init_regs' was not declared. Should it be static?
drivers/clk/meson/meson8b.c: In function 'meson8b_clkc_probe':
drivers/clk/meson/meson8b.c:1052:14: warning: unused variable 'clk' [-Wunused-variable]

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-14 15:36:31 -07:00
Stephen Boyd cc4d07a411 i.MX clock misc updates for 4.17:
- A correction on i.MX6SX CKO clock mux options.
  - A fix on i.MX7D Video PLL clock tree to include the missing dividers.
  - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf
    clock for i.MX6ULL.
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Merge tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clock misc updates from Shawn Guo:

 - A correction on i.MX6SX CKO clock mux options.
 - A fix on i.MX7D Video PLL clock tree to include the missing dividers.
 - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf
   clock for i.MX6ULL.

* tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6ull: Add epdc_podf instead of sim_podf
  clk: imx: imx7d: correct video pll clock tree
  clk: imx: imx6sx: update cko mux options
2018-03-14 15:14:08 -07:00
Stephen Boyd a91f77ef15 clk: hisilicon: Mark phase_ops static
Sparse rightfully complains:

drivers/clk/hisilicon/clk-hisi-phase.c:88:22: warning: symbol 'clk_phase_ops' was not declared. Should it be static?
drivers/clk/hisilicon/clk-hisi-phase.c:88:22: warning: symbol 'clk_phase_ops' was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-14 14:34:16 -07:00
Marek Szyprowski 5b23fceec1 clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
FIMC LITE SYSMMU devices are defined in exynos5250.dtsi, but clocks for
them are not instantiated by Exynos5250 clock provider driver. Add needed
definitions for those clocks to fix IOMMU probe failure:

ERROR: could not get clock /soc/sysmmu@13c40000:sysmmu(0)
exynos-sysmmu 13c40000.sysmmu: Failed to get device clock(s)!
exynos-sysmmu: probe of 13c40000.sysmmu failed with error -38
ERROR: could not get clock /soc/sysmmu@13c50000:sysmmu(0)
exynos-sysmmu 13c50000.sysmmu: Failed to get device clock(s)!
exynos-sysmmu: probe of 13c50000.sysmmu failed with error -38

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: bfed1074f2 ("clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks")
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-14 12:12:11 +01:00
Derek Basehore 4ee3fd4abe clk: rockchip: Add 1.6GHz PLL rate for rk3399
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-14 00:37:22 +01:00
Jacopo Mondi 1e04204eff clk: renesas: r8a77965: Replace DU2 clock
R-Car M3-N does not have the DU2 unit but it has DU3 instead.
Fix the module clock definition to reflect that.

Fixes: 7ce36da900 ("clk: renesas: cpg-mssr: Add support for R-Car M3-N")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-13 17:10:45 +01:00
Shawn Lin 60cf09e45f clk: rockchip: Restore the clock phase after the rate was changed
There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-13 13:06:15 +01:00
Jerome Brunet 5b13ef64ee clk: meson: clean-up clk81 clocks
clk81 is a composite clock which parents all the peripheral clocks of the
platform. It is a critical clock which is used as provided by the
bootloader. We don't want to change its rate or reparent it, ever.

Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't
gate so the flag is useless, and the gate is already critical, so the
clock won't ever be unused.

Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is
read-only.

Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for
the divider. A peripheral clock should not try to change the rate of
clk81. Stopping the rate propagation is good way to make sure such request
would be ignored.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:10:00 +01:00
Jerome Brunet 05f814402d clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.

Add these gates to enable/disable the clocks when required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:58 +01:00
Jerome Brunet 513b67ac39 clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:56 +01:00
Jerome Brunet 093c3fac46 clk: meson: axg: add hifi pll clock
Add the hifi pll to the axg clock controller. This clock maybe used as an
input of the axg audio clock controller. It uses the same settings table
as the gp0 pll but has a frac parameter allowing more precision.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:54 +01:00
Jerome Brunet 0a1be867b9 clk: meson: add ROUND_CLOSEST to the pll driver
Provide an option for the pll driver to round to the rate closest to the
requested rate, instead of systematically rounding down.

This may allow the provided rate to be closer to the requested rate when
rounding up is not an issue

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:49 +01:00
Jerome Brunet c77de0e5c9 clk: meson: add gp0 frac parameter for axg and gxl
Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:47 +01:00
Jerome Brunet 8289aafa4f clk: meson: improve pll driver results with frac
Finding the appropriate settings of meson plls is too tricky to be done
entirely at runtime, using calculation only. Many combination of m, n
and od won't lock which is why we are using a table for this.  However,
for plls having a fractional parameters, it is possible to improve on
the result provided by the table by calculating the frac parameter.

This change adds the calculation of frac when the parameter is available
and the rate provided by the table is not an exact match for the
requested rate.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:45 +01:00
Jerome Brunet c178b003bf clk: meson: remove special gp0 lock loop
After testing, it appears that the gxl (and axg) does not require the
special locking/reset loop which was initially added for it.

All the values present in the gxl table can locked with the simple lock
checking loop.

The change switches the gxl and axg gp0 back to the simple lock checking
loop and removes the code no longer required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:38 +01:00
Jerome Brunet 117863e842 clk: meson: poke pll CNTL last
Poking CNTL first may take the PLL out of reset while we are still
applying the initial settings, including the filter values
initialization. This is the case for the axg and gxl gp0 pll.

Doing this poke last ensures the pll stays in reset while the initial
settings are applied.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:36 +01:00
Jerome Brunet 2eab2d7cab clk: meson: add fractional part of meson8b fixed_pll
Add the missing frac parameter to the meson8b fixed_pll. It seems to be
always on this platform, so the rate remains unchanged

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:33 +01:00
Jerome Brunet 4162dd5b3a clk: meson: use hhi syscon if available
On gxbb and axg, try to get the hhi regmap from the parent DT node, which
should be the HHI system controller once the necessary changes have been
made in amlogic's DTs

Until then, if getting regmap through the system controller fails, the
clock controller will fall back to the old way, requesting memory region
directly and then registering the regmap itself.

This should allow a smooth transition to syscon

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:04 +01:00
Jerome Brunet 03a6519e9c clk: meson: remove obsolete cpu_clk
meson8b cpu_clk has been replaced by a set of divider and mux clocks.
meson_cpu_clk is no longer used and can be removed

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:04 +01:00
Jerome Brunet 251b6fd38b clk: meson: rework meson8b cpu clock
Instead of migrating meson cpu_clk to clk_regmap, like the other meson
clock drivers, we take advantage of the massive rework to get rid of it
completely, and solve (the first part) of the related FIXME notice.

As pointed out in the code comments, the cpu_clk should be modeled with
dividers and muxes it is made of, instead of one big composite clock.

The cpu_clk was not working correctly to enable dvfs on meson8b. It hangs
quite often when changing the cpu clock rate. This new implementation,
based on simple elements improves the situation but the platform will
still hang from time to time. This is not acceptable so, until we can
make the mechanism around the cpu clock stable, the cpu clock subtree
has been put in read-only mode, preventing any change of the cpu clock

The notifier and read-write operation will be added back when we have a
solution to the problem.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet d610b54f77 clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet 722825dcd5 clk: meson: migrate plls clocks to clk_regmap
Rework meson pll driver to use clk_regmap and move meson8b, gxbb and
axg's clock using meson_clk_pll to clk_regmap.

This rework is not just about clk_regmap, there a serious clean-up of
the driver code:
* Add lock and reset field: Previously inferred from the n field.
* Simplify the reset logic: Code seemed to apply reset differently but
  in fact it was always the same -> assert reset, apply params,
  de-assert reset. The 2 lock checking loops have been kept for now, as
  they seem to be necessary.
* Do the sequence of init register pokes only at .init() instead of in
  .set_rate(). Redoing the init on every set_rate() is not necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet 88a4e12836 clk: meson: migrate the audio divider clock to clk_regmap
Rework meson audio divider driver to use clk_regmap and move gxbb
clock using meson_clk_audio_divider to clk_regmap.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:02 +01:00
Jerome Brunet c763e61ae8 clk: meson: migrate mplls clocks to clk_regmap
Rework meson mpll driver to use clk_regmap and move meson8b, gxbb
and axg clocks using meson_clk_mpll to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:02 +01:00
Jerome Brunet f510c32a6a clk: meson: add regmap helpers for parm
Meson clock drivers are using struct parm to describe each field of the
clock provider. Providing helpers to access these fields with regmap
helps to keep drivers readable

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:01 +01:00
Jerome Brunet 2513a28c10 clk: meson: migrate muxes to clk_regmap
Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap
Also remove a few useless tables in the process

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:01 +01:00
Jerome Brunet f06ddd2852 clk: meson: migrate dividers to clk_regmap
Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet 7f9768a540 clk: meson: migrate gates to clk_regmap
Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet 161f6e5baa clk: meson: add regmap to the clock controllers
This change registers a regmap in meson8b, gxbb and axg controllers.
The clock are still accessing their registers directly through iomem.
Once all clocks handled by these controllers have been move to regmap,
the regmap register will be removed and replaced with a syscon request.

This is needed because other drivers, such as the HDMI driver, need to
access the HHI register region

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet 1f932d9971 clk: meson: remove superseded aoclk_gate_regmap
aoclk_gate_regmap has been replaced by meson's clk_regmap.
It is no longer necessary so, remove it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:59 +01:00
Jerome Brunet 81c7fcac9b clk: meson: switch gxbb ao_clk to clk_regmap
Drop the gxbb ao specific regmap based clock and use the
meson clk_regmap based clock instead.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:59 +01:00
Jerome Brunet ea11dda9e0 clk: meson: add regmap clocks
Meson clock controllers need to move the classical iomem registers to
regmap. This is triggered because the HHI controllers found on the GXBB
and GXL host more than just clocks. To properly handle this, we would
like to migrate HHI to syscon. Also GXBB AO clock controller already use
regmap, AXG AO and Audio clock controllers will as well.

The purpose of this change is to provide a common structure to these
meson controllers (and possibly others) for regmap based clocks.

This change provides the basic gate, mux and divider, based on the
helpers provided by the related generic clocks

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:58 +01:00
Jerome Brunet 7b174c5ebe clk: meson: remove obsolete comments
Over time things changes in CCF and issues have been fixed in meson
controllers.

Now, clk81 is decently modeled by read-only PLLs, a mux, a divider
and a gate. We can remove the FIXME comments related to clk81.
Also remove the comment about devm_clk_hw_register, as there is
apparently nothing wrong with it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:58 +01:00
Jerome Brunet 14bd7b9c8d clk: meson: only one loop index is necessary in probe
We don't need several loop index variables in the probe function
This is far from being critical but since we are doing a vast
rework of meson clock controllers, now is the time to lower the
entropy a bit

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:57 +01:00
Jerome Brunet 332b32a232 clk: meson: use devm_of_clk_add_hw_provider
There is no remove callbacks in meson's clock controllers and
of_clk_del_provider is never called if of_clk_add_hw_provider has been
executed, introducing a potential memory leak.
Fixing this by the using the devm variant.

In reality, the leak would never happen since these controllers are
never unloaded once in use ... still, this is worth cleaning.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:57 +01:00
Jerome Brunet 323346d31d clk: meson: use dev pointer where possible
The 'dev' pointer is directly available in gxbb and axg clock
controller, so consistently use it instead of going the through the
'pdev' pointer once in while

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:56 +01:00
Neil Armstrong 867a5a129a Merge branch 'topic/pll-fixes' into next/drivers 2018-03-13 10:03:12 +01:00
Leonard Crestez a5510399e9 clk: imx6ull: Add epdc_podf instead of sim_podf
This is one of the differences between 6ul and 6ull: imx6ull has no sim
but has epdc and this clock is redefined on the same bit.

This can be verified in the Reference Manuals.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-13 09:03:14 +08:00
Wei Yongjun 55c19eee3b clk: qcom: msm8916: Fix return value check in qcom_apcs_msm8916_clk_probe()
In case of error, the function dev_get_regmap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 81ac38847a ("clk: qcom: Add APCS clock controller support")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:14:24 -07:00
Wei Yongjun 9903e41ae1 clk: hisilicon: hi3660:Fix potential NULL dereference in hi3660_stub_clk_probe()
platform_get_resource() may return NULL, add proper check to
avoid potential NULL dereferencing.

This is detected by Coccinelle semantic patch.

@@
expression pdev, res, n, t, e, e1, e2;
@@

res = platform_get_resource(pdev, t, n);
+ if (!res)
+   return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);

Fixes: 4f16f7ff3b ("clk: hisilicon: Add support for Hi3660 stub clocks")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:12:26 -07:00
Stephen Boyd 56e1ee3539 Merge branch 'clk-helpers' (early part) into clk-fixes
* 'clk-helpers' (early part):
  clk: fix determine rate error with pass-through clock
2018-03-12 15:10:54 -07:00
Jerome Brunet f5edaefee2 clk: qcom: use divider_ro_round_rate helper
There is now an helper function to round the rate when the
divider is read-only. Let's use it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:27 -07:00
Jerome Brunet b15ee490e1 clk: divider: read-only divider can propagate rate change
When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the
register shall be left un-touched, but it does not mean the clock
should stop rate propagation if CLK_SET_RATE_PARENT is set

This is properly handled in qcom clk-regmap-divider but it was not in
the generic divider

To fix this situation, introduce a new helper function
divider_ro_round_rate, on the same model as divider_round_rate.

Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-By: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:26 -07:00
Jerome Brunet 541debae0a clk: call the clock init() callback before any other ops callback
Some clocks may need to initialize things, whatever it is, before
being able to properly operate. Move the .init() call before any
other callback, such recalc_rate() or get_phase(), so the clock
is properly setup before being used.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:24 -07:00
Jerome Brunet 77deb66d26 clk: mux: add helper function for index/value translation
Add helper functions for the translation between parent index and
register value in the generic multiplexer function. The purpose of
this change is avoid duplicating the code in other clock providers,
using the same generic logic.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:23 -07:00
Jerome Brunet e6d3cc7b1f clk: divider: export clk_div_mask() helper
Export clk_div_mask() in clk-provider header so every clock providers
derived from the generic clock divider may share the definition instead
of redefining it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:23 -07:00
Jerome Brunet 04bf9ab335 clk: fix determine rate error with pass-through clock
If we try to determine the rate of a pass-through clock (a clock which
does not implement .round_rate() nor .determine_rate()),
clk_core_round_rate_nolock() will directly forward the call to the
parent clock. In the particular case where the pass-through actually
does not have a parent, clk_core_round_rate_nolock() will directly
return 0 with the requested rate still set to the initial request
structure. This is interpreted as if the rate could be exactly achieved
while it actually cannot be adjusted.

This become a real problem when this particular pass-through clock is
the parent of a mux with the flag CLK_SET_RATE_PARENT set. The
pass-through clock will always report an exact match, get picked and
finally error when the rate is actually getting set.

This is fixed by setting the rate inside the req to 0 when core is NULL
in clk_core_round_rate_nolock() (same as in __clk_determine_rate() when
hw is NULL)

Fixes: 0f6cc2b8e9 ("clk: rework calls to round and determine rate callbacks")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 15:10:22 -07:00
Stephen Boyd 91584eb51b Merge branch 'clk-phase' into clk-fixes
* clk-phase:
  clk: update cached phase to respect the fact when setting phase
2018-03-12 15:09:03 -07:00
Stephen Boyd bd13c6cbd3 TI SoC clock fixes for 4.16.
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Merge tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm into clk-fixes

Pull TI SoC clock fixes for 4.16 from Tero Kristo:

* tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm:
  clk: ti: am43xx: add set-rate-parent support for display clkctrl clock
  clk: ti: am33xx: add set-rate-parent support for display clkctrl clock
  clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
2018-03-12 15:07:42 -07:00
Stephen Boyd a88bb86d58 i.MX clock fixes for 4.16:
- Update i.MX5 clock driver to register UART4/5 clock only on i.MX50
    and i.MX53.  It fixes a kernel warning seen on i.MX53, caused by
    commit 59dc3d8c86 ("clk: imx51: uart4, uart5 gates only exist on
    imx50, imx53").
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Merge tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

Pull i.MX clock fixes for 4.16 from Shawn Guo:

 - Update i.MX5 clock driver to register UART4/5 clock only on i.MX50
   and i.MX53.  It fixes a kernel warning seen on i.MX53, caused by
   commit 59dc3d8c86 ("clk: imx51: uart4, uart5 gates only exist on
   imx50, imx53").

* tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx51-imx53: Fix UART4/5 registration on i.MX50 and i.MX53
2018-03-12 15:06:38 -07:00
Stephen Boyd 957a42e859 Allwinner clock fixes for 4.16
A critical fix for the A31 sunxi-ng clock driver. The CLK_OUT clocks
 had definitions paired with the incorrect type of clk ops. This results
 in a serious oops starting with commit 946797aa3f ("clk: sunxi-ng:
 Support fixed post-dividers on MP style clocks"), which exposed the
 incorrect clk ops when it added a new field to the data structures,
 which then nudged the underlying (compatible but incorrect) data
 structures out of alignment.
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Merge tag 'sunxi-clk-fixes-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clock fixes for 4.16 from Chen-Yu Tsai:

A critical fix for the A31 sunxi-ng clock driver. The CLK_OUT clocks
had definitions paired with the incorrect type of clk ops. This results
in a serious oops starting with commit 946797aa3f ("clk: sunxi-ng:
Support fixed post-dividers on MP style clocks"), which exposed the
incorrect clk ops when it added a new field to the data structures,
which then nudged the underlying (compatible but incorrect) data
structures out of alignment.

* tag 'sunxi-clk-fixes-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops
2018-03-12 15:05:49 -07:00
Jerome Brunet 99652a469d clk: migrate the count of orphaned clocks at init
The orphan clocks reparents should migrate any existing count from the
orphan clock to its new acestor clocks, otherwise we may have
inconsistent counts in the tree and end-up with gated critical clocks

Assuming we have two clocks, A and B.
* Clock A has CLK_IS_CRITICAL flag set.
* Clock B is an ancestor of A which can gate. Clock B gate is left
  enabled by the bootloader.

Step 1: Clock A is registered. Since it is a critical clock, it is
enabled. The clock being still an orphan, no parent are enabled.

Step 2: Clock B is registered and reparented to clock A (potentially
through several other clocks). We are now in situation where the enable
count of clock A is 1 while the enable count of its ancestors is 0, which
is not good.

Step 3: in lateinit, clk_disable_unused() is called, the enable_count of
clock B being 0, clock B is gated and and critical clock A actually gets
disabled.

This situation was found while adding fdiv_clk gates to the meson8b
platform.  These clocks parent clk81 critical clock, which is the mother
of all peripheral clocks in this system. Because of the issue described
here, the system is crashing when clk_disable_unused() is called.

The situation is solved by reverting
commit f8f8f1d044 ("clk: Don't touch hardware when reparenting during registration").
To avoid breaking again the situation described in this commit
description, enabling critical clock should be done before walking the
orphan list. This way, a parent critical clock may not be accidentally
disabled due to the CLK_OPS_PARENT_ENABLE mechanism.

Fixes: f8f8f1d044 ("clk: Don't touch hardware when reparenting during registration")
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-12 11:10:47 -07:00
Marcel Ziswiler c35b518f9b clk: tegra: Fix pll_u rate configuration
Turns out latest upstream U-Boot does not configure/enable pll_u which
leaves it at some default rate of 500 kHz:

root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep pll_u
       pll_u                  3        3        0      500000          0

Of course this won't quite work leading to the following messages:

[    6.559593] usb 2-1: new full-speed USB device number 2 using tegra-
ehci
[   11.759173] usb 2-1: device descriptor read/64, error -110
[   27.119453] usb 2-1: device descriptor read/64, error -110
[   27.389217] usb 2-1: new full-speed USB device number 3 using tegra-
ehci
[   32.559454] usb 2-1: device descriptor read/64, error -110
[   47.929777] usb 2-1: device descriptor read/64, error -110
[   48.049658] usb usb2-port1: attempt power cycle
[   48.759475] usb 2-1: new full-speed USB device number 4 using tegra-
ehci
[   59.349457] usb 2-1: device not accepting address 4, error -110
[   59.509449] usb 2-1: new full-speed USB device number 5 using tegra-
ehci
[   70.069457] usb 2-1: device not accepting address 5, error -110
[   70.079721] usb usb2-port1: unable to enumerate USB device

Fix this by actually allowing the rate also being set from within
the Linux kernel.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12 13:59:06 +01:00
Dmitry Osipenko c485ad63ab clk: tegra: Specify VDE clock rate
Currently VDE clock rate is determined by clock config left from
bootloader, let's not rely on it and explicitly specify the clock
rate in the CCF driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12 13:59:06 +01:00
Dmitry Osipenko ea141d5819 clk: tegra20: Correct PLL_C_OUT1 setup
PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12 13:59:05 +01:00
Dmitry Osipenko 2dcabf053c clk: tegra: Mark HCLK, SCLK and EMC as critical
Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <stable@vger.kernel.org> # v4.16
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12 13:58:58 +01:00
Sylwester Nawrocki 948e068454 clk: samsung: exynos5420: Add more entries to EPLL rate table
Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-12 11:23:27 +01:00
Sylwester Nawrocki 06255a9279 clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
This allows changing the EPLL output frequency through the audio subsystem
clock tree leaf clocks. This change is needed to support audio on the HDMI
interface on Peach-Pi(t) Chromebook.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-12 11:20:30 +01:00
tianshuliang d1b0399543 clk: hi3798cv200: add emmc sample and drive clock
It adds eMMC sample clock HISTB_MMC_SAMPLE_CLK and drive clock
HISTB_MMC_DRV_CLK support for Hi3798cv200 SoC.

Signed-off-by: tianshuliang <tianshuliang@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-03-12 15:56:58 +08:00
tianshuliang 811f67cc16 clk: hisilicon: add hisi phase clock support
Add a phase clock type for HiSilicon SoCs,which supports
clk_set_phase operation.

Signed-off-by: tianshuliang <tianshuliang@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-03-12 15:56:40 +08:00
Shawn Lin 7f95beea36 clk: update cached phase to respect the fact when setting phase
It's found that the final phase set by driver doesn't match that of
the output from clk_summary:

dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346
mmc0: new ultra high speed SDR104 SDIO card at address 0001

cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample	0        1        0    50000000 0 0

It seems the cached core->phase isn't updated after the clk was
registered. So fix this issue by updating the core->phase if setting
phase successfully.

Fixes: 9e4d04adeb ("clk: add clk_core_set_phase_nolock function")
Cc: Stable <stable@vger.kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 18:21:19 -07:00
Gabriel Fernandez 3a43006783 clk: stm32mp1: add Debug clocks
RCC manages clock for debug and trace.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:34 -07:00
Gabriel Fernandez 44cd455a8e clk: stm32mp1: add MCO clocks
Two micro-controller clock output (MCO) pins are available:
MCO1 and MCO2.
For each output, it is possible to select a clock source.
The selected clock can be divided thanks to configurable
prescaler.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:34 -07:00
Gabriel Fernandez 2c87c9d331 clk: stm32mp1: add RTC clock
This patch adds the RTC clock.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez 1f80590b6b clk: stm32mp1: add Peripheral & Kernel Clocks
Each peripheral requires a bus interface clock.
Some peripherals need also a dedicated clock for their communication
interface, this clock is generally asynchronous with respect to the bus
interface clock (peripheral clock), and is named kernel clock.

For each IP, Peripheral clock and Kernel are generally gating with same
gate. Also, Kernel clocks can share a same multiplexer.
This patch introduces a mechanism to manage a gate with several
clocks and to manage a shared multiplexer (mgate and mmux).

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez 799b6a125e clk: stm32mp1: add Kernel timers
This patch adds Kernel timers.
This patch adds timers kernel clock.
Timers are gather into two groups corresponding to the APB bus
they are attached to.
Each group has its own prescaler, managed in this patch.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez e51d297e9a clk: stm32mp1: add Sub System clocks
The RCC handles three sub-system clocks: ck_mpuss, ck_axiss
and ck_mcuss.
This patch adds also some MUX system and several prescalers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez a97703c59f clk: stm32mp1: add Post-dividers for PLL
Each PLL has 3 outputs with post-dividers.

pll1_p is dedicated for Cortex-A7
pll1_q is not connected
pll1_r is not connected

pll2_p is dedicated for AXI
pll2_q is dedicated for GPU
pll2_r is dedicated for DDR

pll3_p is dedicated for mcu
pll3_q is for Peripheral Kernel Clock
pll3_r is for Peripheral Kernel Clock

pll4_p is for Peripheral Kernel Clock
pll4_q is for Peripheral Kernel Clock
pll4_r is for Peripheral Kernel Clock

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez c6cf4d3248 clk: stm32mp1: add PLL clocks
STMP32MP1 has 4 PLLs.
PLL supports integer and fractional mode.
Each PLL has 3 output dividers (p, q, r)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez dc32eaac49 clk: stm32mp1: add Source Clocks for PLLs
This patch adds source clocks for PLLs
This patch also introduces MUX clock API.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:33 -07:00
Gabriel Fernandez 8e6c27c0d7 clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators
MP1 Gate is a gate with a set and a clear register.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:32 -07:00
Gabriel Fernandez 9bee94e7b7 clk: stm32mp1: Introduce STM32MP1 clock driver
This patch introduces the mechanism to probe stm32mp1 driver.
It also defines registers definition.
This patch also introduces the generic mechanism to register
a clock (a simple gate, divider and fixed factor).

All clocks will be defined in one table.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-11 15:40:32 -07:00
Peter De Schrijver e403d00573 clk: tegra: MBIST work around for Tegra210
Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a
domain. The reason is that the logic responsible for resetting the memory
built-in self test mode can come up in an undefined state because its
clock is gated by a second level clock gate (SLCG). Work around this by
making sure the logic will get some clock edges by ensuring the relevant
clock is enabled and temporarily override the relevant SLCGs.
Unfortunately for some IP blocks, the control bits for overriding the
SLCGs are not in CAR, but in the IP block itself. This means we need to
map a few extra register banks in the clock code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

fixup mbist
2018-03-08 19:18:08 +01:00
Peter De Schrijver cbfc8d0a85 clk: tegra: add fence_delay for clock registers
To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08 15:26:54 +01:00
Peter De Schrijver 89e423c3f1 clk: tegra: Add la clock for Tegra210
This clock is needed by the memory built-in self test work around.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08 15:26:11 +01:00
Tero Kristo 762790b752 clk: ti: am43xx: add set-rate-parent support for display clkctrl clock
Display driver assumes it can use clk_set_rate for the display clock
via set-rate-parent mechanism, so add the flag for this to id.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2018-03-08 12:14:44 +02:00
Tero Kristo 49159a9dc3 clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
Certain clkctrl clocks, notably the display ones, use the
CLK_SET_RATE_PARENT feature extensively. Add support for this flag
to the clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Jyri Sarha <jsarha@ti.com>
2018-03-08 12:14:43 +02:00
Tero Kristo c083dc5f37 clk: ti: am33xx: add set-rate-parent support for display clkctrl clock
Display driver assumes it can use clk_set_rate for the display clock
via set-rate-parent mechanism, so add the flag for this to it.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Jyri Sarha <jsarha@ti.com>
2018-03-08 12:14:43 +02:00
Tero Kristo 3c13933c60 clk: keystone: sci-clk: add support for dynamically probing clocks
Currently, the driver contains a large hints table for clocks that exist
on a device, however, it is possible to probe the clocks from the firmware
also. Add support for this, and drop the clock hints table support from
the driver completely. This causes the driver to send a few extra sci-clk
messages during boot, basically one extra for each device that exists on
the SoC; on K2G this is approx 80.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
2018-03-08 11:43:15 +02:00
Tero Kristo ee2fc3c5ca clk: ti: add support for clock latching to mux clocks
Latching the clock settings is needed with certain clocks, where
the setting is "cached" in HW before doing the actual re-programming
of the clock source. This patch adds support for clock latching to
the mux clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-03-08 11:42:05 +02:00
Tero Kristo b44a03008d clk: ti: add support for clock latching to divider clocks
Latching the clock settings is needed with certain clocks, where
the setting is "cached" in HW before doing the actual re-programming
of the clock source. This patch adds support for clock latching to
the divider clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-03-08 11:42:04 +02:00
Tero Kristo e31922eda1 clk: ti: add generic support for clock latching
Certain clocks require latching to be done, so that the actual
settings get updated on the HW that generates the clock signal.
One example of such a clock is the dra76x GMAC DPLL H14 output,
which requires its divider settings to be latched when updated.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-03-08 11:42:04 +02:00
Tero Kristo 4902c2025b clk: ti: add support for register read-modify-write low-level operation
Useful for changing few bits on a register, this makes sure for example
that the operation is done atomically in case of syscon.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-03-08 11:42:04 +02:00
Marek Szyprowski edcefb96fb clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP1 block require special handling for power domain
turn on/off sequences. Till now this was handled by Exynos power domain
driver, but that approach was limited only to some special cases. This
patch moves handling of those operations to clock controller driver.
This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-06 17:39:40 +01:00
Marek Szyprowski ec4016ff6e clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP, GSC and MFC blocks require special handling for
power domain turn on/off sequences. Till now this was handled by Exynos
power domain driver, but that approach was limited only to some special
cases. This patch moves handling of those operations to clock controller
driver. This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5420 driver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-06 17:39:16 +01:00
Marek Szyprowski b06a532bf1 clk: samsung: Add Exynos5 sub-CMU clock driver
Exynos5250/5420/5800 have only one clock controller, but some of their
clock depends on respective power domains. Handling integration of clock
controller and power domain can be done using runtime PM feature of CCF
framework. This however needs a separate struct device for each power
domain. This patch adds such separate driver for a group of such clocks,
which can be instantiated more than once, each time for a different
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-06 17:38:46 +01:00
Shawn Lin 4bf59902b5 clk: rockchip: Prevent calculating mmc phase if clock rate is zero
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05 21:37:13 +01:00
Shawn Lin fd3cbbfb76 clk: rockchip: Free the memory on the error path
rockchip_clk_register_branch() and rockchip_clk_register_frac_branch()
should free the memory internally when seeing any failure.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-02 08:51:03 +01:00
Jernej Skrabec 55de0f31df
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-02 08:42:30 +01:00
Jernej Skrabec b1a1ad4b75
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
Some units have to be able to set it's own clock precisely to work
correctly. Allow them to do so by adding CLK_SET_RATE_PARENT flag.

Add this flag to DE, TCON and HDMI clocks.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-02 08:42:27 +01:00
Jernej Skrabec 4fd8ae912f
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.

Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on right
factors. For example, when N = 4 and M = 1, output is stable and when N
= 8 and M = 2, it's not.

BSP clock driver suggest that minimum stable frequency is 192 MHz. That
would also be in line with A64 SoC, which has similar periphery.

Set minimal video PLL rate for H3/H5 to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-02 08:42:20 +01:00
Jernej Skrabec 2d2b61c13a
clk: sunxi-ng: Add check for minimal rate to NM PLLs
Some NM PLLs doesn't work well when their output clock rate is set below
certain rate.

Add support for that constrain.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-02 08:42:14 +01:00
Anson Huang b716aad97e clk: imx: imx7d: correct video pll clock tree
There is a test divider and post divider in video PLL,
test divider is placed before post divider, all clocks
that can select parent from video PLL should be from
post divider, NOT from pll_video_main, below are
clock tree dump before and after this patch:

Before:
pll_video_main
   pll_video_main_bypass
      pll_video_main_clk
         lcdif_pixel_src
            lcdif_pixel_cg
               lcdif_pixel_pre_div
                  lcdif_pixel_post_div
                     lcdif_pixel_root_clk
After:
pll_video_main
   pll_video_main_bypass
      pll_video_main_clk
         pll_video_test_div
            pll_video_post_div
               lcdif_pixel_src
                  lcdif_pixel_cg
                     lcdif_pixel_pre_div
                        lcdif_pixel_post_div
                           lcdif_pixel_root_clk

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-01 08:13:38 +08:00
Sudeep Holla 6d6a1d82ea clk: add support for clocks provided by SCMI
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCMI
protocol.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2018-02-28 16:37:57 +00:00
Stefan Agner 1691cc375a clk: imx: imx7d: add the Keypad Port module clock
According to the i.MX7D Reference Manual, the Keypad Port module
(KPP) requires this clock gate to be enabled.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28 14:43:00 +08:00
Rui Miguel Silva baf15cbf54 clk: imx7d: add CAAM clock
Add CAAM clock so that we could use the Cryptographic Acceleration and
Assurance Module (CAAM) hardware block.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: "Horia Geantă" <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28 09:17:41 +08:00
Jianguo Sun 80f8ce5895 clk: hi3798cv200: add COMBPHY0 clock support
The clock COMBPHY1 has already been supported by hi3798cv200 driver,
but COMBPHY0 is missing.  It adds COMBPHY0 clock support.

Since the mux table is being shared by COMBPHY0 and COMBPHY1, it renames
comphy1_mux_p and comphy1_mux_table a bit to drop instance number '1'
from there.

Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-02-27 09:19:12 +08:00
Shawn Guo a44d1f531a clk: hi3798cv200: fix define indentation
It's a coding-style fix, which corrects the indentation for all those
clock definitions, so that the code looks nicer and new definitions can
be added with a recommended indentation.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-02-27 09:19:12 +08:00
Shawn Guo 50fd588ae4 clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
The clock HISTB_USB2_OTG_UTMI_CLK is defined by device tree bindings in
include/dt-bindings/clock/histb-clock.h, but hasn't been supported by
hi3798cv200 clock driver.  Let's add the support for it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-02-27 09:19:12 +08:00
Younian Wang 47629f6765 clk: hi3798cv200: correct IR clock parent
The IR clock is sourced from '24m' rather than '100m'.  Correct it.

Signed-off-by: Younian Wang <wangyounian@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-02-27 09:19:12 +08:00