Граф коммитов

63 Коммитов

Автор SHA1 Сообщение Дата
Josh Boyer e3e414bcc2 [POWERPC] Conditionally compile e200 and e500 platforms in cputable
The e200 and e500 platforms are separated in various parts of the kernel with
ifdefs, most notably reg_booke.h and traps.c.  The new machine_check rework
requires them to be similarly separated in cputable.c to avoid compile errors.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-24 08:44:47 -06:00
Valentine Barshak b2be3b1529 [POWERPC] 4xx: Correct 440GRx machine_check callback
Correct the PowerPC 440GRx machine check callback.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-23 13:26:10 -06:00
Benjamin Herrenschmidt 47c0bd1ae2 [POWERPC] Reworking machine check handling and Fix 440/440A
This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs->trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-23 13:11:59 -06:00
Li Yang a58d52443f [POWERPC] add e300c4 entry to cputable
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 13:57:17 -06:00
Valentine Barshak d1dfc35d3a [POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue.
PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since
they have identical cores. However, FPU is not supported on GR(x) and
enabling APU instruction broadcast in the CCR0 register (to enable FPU)
may cause unpredictable results. There's no safe way to detect FPU
support at runtime. This patch provides a workarund for the issue.

We use a POWER6 "logical PVR approach". First, we identify all EP(x)
and GR(x) processors as GR(x) ones (which is safe). Then we check
the device tree cpu path. If we have a EP(x) processor entry,
we call identify_cpu again with PVR | 0x8. This bit is always 0
in the real PVR. This way we enable FPU only for 440EP(x).

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-11-01 07:13:43 -05:00
Stefan Roese 5d8476c8fa [POWERPC] 4xx: Add AMCC 405EX support to cputable.c
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-11 15:01:22 -05:00
Paul Mackerras 87a72f9e17 [POWERPC] Fix performance monitor on machines with logical PVR
Some IBM machines supply a "logical" PVR (processor version register)
value in the device tree in the cpu nodes rather than the real PVR.
This is used for instance to indicate that the processors in a POWER6
partition have been configured by the hypervisor to run in POWER5+
mode rather than POWER6 mode.  To cope with this, we call identify_cpu
a second time with the logical PVR value (the first call is with the
real PVR value in the very early setup code).

However, POWER5+ machines can also supply a logical PVR value, and use
the same value (the value that indicates a v2.04 architecture
compliant processor).  This causes problems for code that uses the
performance monitor (such as oprofile), because the PMU registers are
different in POWER6 (even in POWER5+ mode) from the real POWER5+.

This change works around this problem by taking out the PMU
information from the cputable entries for the logical PVR values, and
changing identify_cpu so that the second call to it won't overwrite
the PMU information that was established by the first call (the one
with the real PVR), but does update the other fields.  Specifically,
if the cputable entry for the logical PVR value has num_pmcs == 0,
none of the PMU-related fields get used.

So that we can create a mixed cputable entry, we now make cur_cpu_spec
point to a single static struct cpu_spec, and copy stuff from
cpu_specs[i] into it.  This has the side-effect that we can now make
cpu_specs[] be initdata.

Ultimately it would be good to move the PMU-related fields out to a
separate structure, pointed to by the cputable entries, and change
identify_cpu so that it saves the PMU info pointer, copies the whole
structure, and restores the PMU info pointer, rather than identify_cpu
having to list all the fields that are *not* PMU-related.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2007-10-11 21:37:50 +10:00
Valentine Barshak 340ffd267c [POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround
Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:18 -05:00
Valentine Barshak 8112753bb2 [POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx
The PowerPC 440EP(x) FPU init is currently done in head_44x
under ifdefs. Since we should support more then one board
in the same kernel, we move FPU initialization code from head_44x
to cpu_setup_44x and add cpu_setup callbacks for 440EP(x).

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:17 -05:00
Valentine Barshak 84e3ad5b91 [POWERPC] 4xx: Introduce cpu_setup functionality to 44x platform
This adds cpu_setup functionality for ppc44x platform.
Low level cpu-spefic initialization routines should be
placed in cpu_setup_44x.S and a callback should be
added to cputable. The cpu_setup is invoked
by identify_cpu() function at early init.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:17 -05:00
Kumar Gala 5e14d21e3f [POWERPC] Add cpu feature for SPE handling
Make it so that SPE support can be determined at runtime.  This is similiar
to how we handle AltiVec.  This allows us to have SPE support built in and
work on processors with and without SPE.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-14 08:53:30 -05:00
Valentine Barshak 15fc993e31 [POWERPC] PowerPC 440EPx: Sequoia board support
AMCC PPC440EPx Sequoia board support.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-09-07 07:49:13 -05:00
Mike Wolf 31a12cece7 [POWERPC] Oprofile support for Power 5++
This adds a new oprofile cpu type for Power 5 revision 3 chips.
The new name is ppc64/power5++ and is used so that the performance
counters can be set up correctly.

Signed-off-by: Mike Wolf <mjw@us.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-11 13:21:46 +10:00
Roland Dreier 333e615483 [POWERPC] Add cputable entry for PowerPC 440SPe Rev. B
When adding the cputable entry for 440SPe Rev. B, we also need to
adjust the existing entries for 440SP Rev. A and 440SPe Rev. B so that
they look more bits of the PVR.  The 440SPe Rev. B has PVR 53421891,
which would match the current 440SP Rev. A pattern of 53xxx891.  To
distinguish between 440SP and 440SPe, we need to use the first three
digits of the PVR, which are respectively 532 and 534.

Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-10 21:53:44 +10:00
Anton Blanchard 2fae4985a1 [POWERPC] Add missing pmc_type fields in cpu_table
A number of cpu_table entries were missing the pmc_type field,
which means that the sysfs entries for the performance monitor
counters don't get created.  This adds them.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-05-22 20:20:56 +10:00
James.Yang 3d372548b4 [POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448.
Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
This prevents needlessly setting M=1 when not SMP.

Signed-off-by: James.Yang <James.Yang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-05-17 21:10:15 +10:00
Olof Johansson 25fc530eed [POWERPC] pasemi: PA6T oprofile support
Oprofile support for PA6T, kernel side.

Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-24 21:31:51 +10:00
Josh Boyer a14c4508f4 [POWERPC] Fix PowerPC 750CL and 750GX CPU features
PowerPC 750CL has high BATs.  The patch below adds a CPU_FTRS_750CL that
includes that.  Without it, the original firmware mappings in the high BATs
aren't cleared which continue to override the linux translations.

It also adds CPU_FTR_COMMON to CPU_FTRS_750GX for completeness.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-24 21:31:47 +10:00
Jake Moilanen cfbff8a380 [POWERPC] 750CL cputable entry
750CL cputable entry from Steve Winiecki.

Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-03-09 15:03:26 +11:00
Olof Johansson 3546e811f1 [POWERPC] No DEEPNAP on 970MP 1.0
970MP rev 1.0 is reported to have nonworking DEEPNAP support, we've had
bug reports of lockups on those machines. Appearantly Apple used them
on some dual-core dual-cpu systems. Rev 1.1 is OK, and that's the one
that all 4-way systems seem to use.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-03-08 04:09:32 +11:00
Stephen Rothwell 40d244d69a [POWERPC] correct a prototype
This rids us of a warning.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-13 15:35:52 +11:00
Olof Johansson 1199919b69 [POWERPC] pasemi: Idle loops
Powersave support on PA6T. Right now it only uses 'doze' mode, and
will default to no savings (spin).

Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07 14:03:22 +11:00
Olof Johansson 1bd2e5ae18 [POWERPC] Add PMC type to cputable
Add cputable entries for which type of PMC implementation the processor
has.

I've only filled in the current 64-bit processors, the unfilled default
value will have same behaviour as before so it can be done over time
as needed.

Also tidy up the dummy_perf implementation a bit, aggregating it into
one function with ifdefs instead of several.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07 14:03:19 +11:00
Kumar Gala a147c5857c [POWERPC] Fix 440SPe CPU table entry
The 440SPe CPU table entry was missing the CPU_FTR_NODSISRALIGN and
really should have been CPU_FTRS_44X.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 02:45:38 -06:00
Kim Phillips aa42c69c67 [POWERPC] Add support for FP emulation for the e300c2 core
The e300c2 has no FPU.  Its MSR[FP] is grounded to zero.  If an attempt
is made to execute a floating point instruction (including floating-point
load, store, or move instructions), the e300c2 takes a floating-point
unavailable interrupt.

This patch adds support for FP emulation on the e300c2 by declaring a
new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are
intercepted and redirected to the ProgramCheck exception path for
correct emulation handling.

(If we run out of CPU_FTR bits we could look to reclaim this bit by adding
support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead)

It adds a nop to the exception path for 32-bit processors with a FPU.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 02:43:30 -06:00
Scott Wood 57933f8fbe [POWERPC] Add the e300c3 core to the CPU table.
This core is used in Freescale's 831x chips.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-04 20:42:06 +11:00
Mike Wolf fecb352f6b [POWERPC] powerpc: Make 970MP detectable by oprofile
Change the oprofile_cpu_type in cputables.c to be ppc64/970MP.  Oprofile
needs to distinquish the MP from other 970 processors so it can add some
new counters specific to the 970MP.

Signed-off-by: Mike Wolf <mjw@us.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-04 20:41:02 +11:00
Paul Mackerras 974a76f513 [POWERPC] Distinguish POWER6 partition modes and tell userspace
This adds code to look at the properties firmware puts in the device
tree to determine what compatibility mode the partition is in on
POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM
entries appropriately.

Specifically, we look at the cpu-version property in the cpu node(s).
If that contains a "logical" PVR value (of the form 0x0f00000x), we
call identify_cpu again with this PVR value.  A value of 0x0f000001
indicates the partition is in POWER5+ compatibility mode, and a value
of 0x0f000002 indicates "POWER6 architected" mode, with various
extensions disabled.  We also look for various other properties:
ibm,dfp, ibm,purr and ibm,spurr.

Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-04 20:40:16 +11:00
Maynard Johnson 18f2190d79 [POWERPC] cell: Add oprofile support
Add PPU event-based and cycle-based profiling support to Oprofile for Cell.

Oprofile is expected to collect data on all CPUs simultaneously.
However, there is one set of performance counters per node.  There are
two hardware threads or virtual CPUs on each node.  Hence, OProfile must
multiplex in time the performance counter collection on the two virtual
CPUs.

The multiplexing of the performance counters is done by a virtual
counter routine.  Initially, the counters are configured to collect data
on the even CPUs in the system, one CPU per node.  In order to capture
the PC for the virtual CPU when the performance counter interrupt occurs
(the specified number of events between samples has occurred), the even
processors are configured to handle the performance counter interrupts
for their node.  The virtual counter routine is called via a kernel
timer after the virtual sample time.  The routine stops the counters,
saves the current counts, loads the last counts for the other virtual
CPU on the node, sets interrupts to be handled by the other virtual CPU
and restarts the counters, the virtual timer routine is scheduled to run
again.  The virtual sample time is kept relatively small to make sure
sampling occurs on both CPUs on the node with a relatively small
granularity.  Whenever the counters overflow, the performance counter
interrupt is called to collect the PC for the CPU where data is being
collected.

The oprofile driver relies on a firmware RTAS call to setup the debug bus
to route the desired signals to the performance counter hardware to be
counted.  The RTAS call must set the routing registers appropriately in
each of the islands to pass the signals down the debug bus as well as
routing the signals from a particular island onto the bus.  There is a
second firmware RTAS call to reset the debug bus to the non pass thru
state when the counters are not in use.

Signed-off-by: Carl Love <carll@us.ibm.com>
Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-04 20:40:14 +11:00
Paul Mackerras 79acbb3ff2 Merge branch 'linux-2.6' into for-linus 2006-12-04 15:59:07 +11:00
Benjamin Herrenschmidt 0909c8c2d5 [POWERPC] Support feature fixups in vdso's
This patch reworks the feature fixup mecanism so vdso's can be fixed up.
The main issue was that the construct:

        .long   label  (or .llong on 64 bits)

will not work in the case of a shared library like the vdso. It will
generate an empty placeholder in the fixup table along with a reloc,
which is not something we can deal with in the vdso.

The idea here (thanks Alan Modra !) is to instead use something like:

1:
        .long   label - 1b

That is, the feature fixup tables no longer contain addresses of bits of
code to patch, but offsets of such code from the fixup table entry
itself. That is properly resolved by ld when building the .so's. I've
modified the fixup mecanism generically to use that method for the rest
of the kernel as well.

Another trick is that the 32 bits vDSO included in the 64 bits kernel
need to have a table in the 64 bits format. However, gas does not
support 32 bits code with a statement of the form:

        .llong  label - 1b  (Or even just .llong label)

That is, it cannot emit the right fixup/relocation for the linker to use
to assign a 32 bits address to an .llong field. Thus, in the specific
case of the 32 bits vdso built as part of the 64 bits kernel, we are
using a modified macro that generates:

        .long   0xffffffff
        .llong  label - 1b

Note that is assumes that the value is negative which is enforced by
the .lds (those offsets are always negative as the .text is always
before the fixup table and gas doesn't support emiting the reloc the
other way around).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-25 11:54:07 +10:00
Benjamin Herrenschmidt 42c4aaadb7 [POWERPC] Consolidate feature fixup code
There are currently two versions of the functions for applying the
feature fixups, one for CPU features and one for firmware features. In
addition, they are both in assembly and with separate implementations
for 32 and 64 bits. identify_cpu() is also implemented in assembly and
separately for 32 and 64 bits.

This patch replaces them with a pair of C functions. The call sites are
slightly moved on ppc64 as well to be called from C instead of from
assembly, though it's a very small change, and thus shouldn't cause any
problem.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-25 11:42:10 +10:00
Jake Moilanen 362ff7b2ac [POWERPC] Add 970GX cputable entry
970GX cputable entry from Steve Winiecki.

Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>

 arch/powerpc/kernel/cputable.c          |   15 +++++++++++++++
 arch/powerpc/oprofile/op_model_power4.c |    2 +-
 include/asm-powerpc/reg.h               |    1 +
 3 files changed, 17 insertions(+), 1 deletion(-)
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-23 18:23:17 +10:00
Olof Johansson 5b43d20a4d [POWERPC] powerpc: Enable DEEPNAP power savings mode on 970MP
Without this patch, on an idle system I get:

cpu-power-0:21.638
cpu-power-1:27.102
cpu-power-2:29.343
cpu-power-3:25.784
Total: 103.8W

With this patch:

cpu-power-0:11.730
cpu-power-1:17.185
cpu-power-2:18.547
cpu-power-3:17.528
Total: 65.0W

If I lower HZ to 100, I can get it as low as:

cpu-power-0:10.938
cpu-power-1:16.021
cpu-power-2:17.245
cpu-power-3:16.145
Total: 60.2W

Another (older) Quad G5 went from 54W to 39W at HZ=250.

Coming back out of Deep Nap takes 40-70 cycles longer than coming back
from just Nap (which already takes quite a while). I don't think it'll
be a performance issue (interrupt latency on an idle system), but in
case someone does measurements feel free to report them.

Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-16 16:32:25 +10:00
Anton Blanchard 99f4861025 [POWERPC] POWER6 has 6 PMCs
Change ->num_pmcs to match the number of PMCs in POWER6.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-16 15:53:30 +10:00
Kim Phillips 6c4a2501d0 [POWERPC] Add initial support for the e300c2 core
Add support for the Freescale e300c2 core found in the MPC832x processor line.

As far as initial kernel support is concerned, the e300c2 core is
identical to the e300c1 found in the mpc834x, except that it's had its
floating point unit chopped off.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 15:24:27 +10:00
Peter Bergner 838fdb4d2d [POWERPC] Add AT_PLATFORM value for Xilinx Virtex-4 FX
Jakub noticed the cputable.c entry for Xilinx Virtex-4 FX was missing
a .platform value, so the AT_PLATFORM value wouldn't be set correctly.
This adds it.

Signed-off-by: Peter Bergner <bergner@vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-09-21 22:54:54 +10:00
Olof Johansson b3ebd1d862 [POWERPC] powerpc: PA6T cputable entry, PVR value
Introduce PWRficient PA6T cputable entries and feature bits.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-09-13 18:39:52 +10:00
Olof Johansson f39b7a55a8 [POWERPC] Cleanup CPU inits
Cleanup CPU inits a bit more, Geoff Levand already did some earlier.

* Move CPU state save to cpu_setup, since cpu_setup is only ever done
  on cpu 0 on 64-bit and save is never done more than once.
* Rename __restore_cpu_setup to __restore_cpu_ppc970 and add
  function pointers to the cputable to use instead. Powermac always
  has 970 so no need to check there.
* Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before
  calling it instead of in it, it's too early to use cputable.
* Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
  everyone but powermac and iSeries use it.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-08-25 13:27:35 +10:00
Jörn Engel 6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Kumar Gala 9ad494f624 powerpc: minor cleanups for mpc86xx
* Remove duplicated cputable entry for 8641 (matches w/7448)
* Removed __init from function prototypes in mpc86xx.h
* Moved pci fixups into board specific code
* Moved mpc86xx_exclude_device to generic mpc86xx pci code
* Fixed sparse warnings in mpc86xx_smp.c
* Removed board specific header include from asm-powerpc/mpc86xx.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-06-28 00:37:45 -05:00
Jon Loeliger 9674ed38d8 [POWERPC] Add 8641 CPU table entry.
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21 15:01:28 +10:00
Anton Blanchard 227318bbde [POWERPC] Remove stale 64bit on 32bit kernel code
Remove some stale POWER3/POWER4/970 on 32bit kernel support.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-15 19:31:26 +10:00
Paul Mackerras fab5db97e4 [PATCH] powerpc: Implement support for setting little-endian mode via prctl
This adds the PowerPC part of the code to allow processes to change
their endian mode via prctl.

This also extends the alignment exception handler to be able to fix up
alignment exceptions that occur in little-endian mode, both for
"PowerPC" little-endian and true little-endian.

We always enter signal handlers in big-endian mode -- the support for
little-endian mode does not amount to the creation of a little-endian
user/kernel ABI.  If the signal handler returns, the endian mode is
restored to what it was when the signal was delivered.

We have two new kernel CPU feature bits, one for PPC little-endian and
one for true little-endian.  Most of the classic 32-bit processors
support PPC little-endian, and this is reflected in the CPU feature
table.  There are two corresponding feature bits reported to userland
in the AT_HWCAP aux vector entry.

This is based on an earlier patch by Anton Blanchard.

Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-09 21:24:15 +10:00
Michael Neuling e78dbc800c [PATCH] powerpc: oprofile support for POWER6
POWER6 moves some of the MMCRA bits and also requires some bits to be
cleared each PMU interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-09 21:24:05 +10:00
Anton Blanchard 87af41beb9 [PATCH] powerpc: add num_pmcs to 970MP cputable entry
The 970MP cputable entry needs a num_pmcs entry for oprofile to work.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-09 21:21:03 +10:00
Geoff Levand b26f100d89 [PATCH] powerpc: remove do-nothing cpu setup routines
Removed the do-nothing routines __setup_cpu_power3 and
__setup_cpu_power4 and replaced them with a null pointer check
in the caller.  Also removed the Cell processor specific
routine __setup_cpu_be which improperly accessed the
hypervisor page size configuration at SPR HID6.

Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-05-19 14:24:18 +10:00
Anton Blanchard 03054d51a7 [PATCH] powerpc: Add cputable entry for POWER6
Add a cputable entry for the POWER6 processor.

The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable
support for that until oprofile is fixed.

Also tell firmware that we know about POWER6.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-04-29 10:56:58 +10:00
Paul Mackerras 5164501794 Merge ../linux-2.6 2006-03-09 14:32:05 +11:00
Benjamin Herrenschmidt aa5cb02143 [PATCH] powerpc: Expose SMT and L1 icache snoop userland features
This patch makes userland aware of the icache snoop capability of the
POWER5 (and possibly others in the future) and of SMT capabilities.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-03 22:00:23 +11:00