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Arnd Bergmann c76edea0e5 Amlogic Drivers updates for v5.18:
- Add support for Amlogic S4 in meson-secure-pwrc power domain driver
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Merge tag 'amlogic-drivers-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/drivers

Amlogic Drivers updates for v5.18:
- Add support for Amlogic S4 in meson-secure-pwrc power domain driver

* tag 'amlogic-drivers-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  soc: s4: Add support for power domains controller
  dt-bindings: power: add Amlogic s4 power domains bindings

Link: https://lore.kernel.org/r/c7471989-d929-c744-c0c3-c8e86eaaa225@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-08 17:06:45 +01:00
Arnd Bergmann 608f7cf3f5 Memory controller drivers for v5.18, part two
1. TI: Two fixes for TI EMIF driver for quite old error path issues (so
    for unlikely scenarios).
 2. Renesas: Document RZ/V2L SoC in bindings.
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Merge tag 'memory-controller-drv-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18, part two

1. TI: Two fixes for TI EMIF driver for quite old error path issues (so
   for unlikely scenarios).
2. Renesas: Document RZ/V2L SoC in bindings.

* tag 'memory-controller-drv-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
  memory: emif: check the pointer temp in get_device_details()
  memory: emif: Add check for setup_interrupts

Link: https://lore.kernel.org/r/20220307082552.55719-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-08 16:50:18 +01:00
Arnd Bergmann d3d009847a AT91 SoC #2 for 5.18:
- SAMA5D29 variant to the SAMA5D2 family in SoC driver.
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Merge tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers

AT91 SoC #2 for 5.18:

- SAMA5D29 variant to the SAMA5D2 family in SoC driver.

* tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: add support in soc driver for new SAMA5D29
  soc: add microchip polarfire soc system controller
  ARM: at91: Kconfig: select PM_OPP
  ARM: at91: PM: add cpu idle support for sama7g5
  ARM: at91: ddr: fix typo to align with datasheet naming
  ARM: at91: ddr: align macro definitions
  ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency

Link: https://lore.kernel.org/r/20220304144216.23340-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-08 16:49:20 +01:00
Arnd Bergmann a2d266a8f1 mmsys: fix compilation by adding SW reset infrastructure
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Merge tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

mmsys: fix compilation by adding SW reset infrastructure

* tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

Link: https://lore.kernel.org/r/e1b90372-a041-db6e-f35a-d17b26069e40@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-07 23:47:48 +01:00
Shunzhou Jiang f2b03c1056 soc: s4: Add support for power domains controller
Add support s4 Power controller. In s4, power control
registers are in secure domain, and should be accessed by smc.

Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220307025357.1368673-3-shunzhou.jiang@amlogic.com
2022-03-07 09:40:39 +01:00
Shunzhou Jiang 40b358f615 dt-bindings: power: add Amlogic s4 power domains bindings
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.

The bindings targets the Amlogic s4, in which the power domains registers
are in secure world.

Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220307025357.1368673-2-shunzhou.jiang@amlogic.com
2022-03-07 09:40:39 +01:00
Mihai Sain def8abbb14 ARM: at91: add support in soc driver for new SAMA5D29
Add detection of new SAMA5D29 by the SoC driver.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220302155329.27668-1-nicolas.ferre@microchip.com
2022-03-04 12:49:22 +01:00
Rex-BC Chen 62dc30150c soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220217082626.15728-2-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-04 10:15:47 +01:00
Lad Prabhakar 69d6941949 dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
Document RZ/V2L RPC-IF bindings. RZ/V2L RPC-IF is identical to one found
on the RZ/G2L SoC. No driver changes are required as generic compatible
string "renesas,rzg2l-rpc-if" will be used as a fallback.

While at it, drop the comment "# RZ/G2L family" for "renesas,rzg2l-rpc-if"
compatible string as this will avoid changing the line for every new SoC
addition.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220301123527.15950-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-03-04 09:09:52 +01:00
Jia-Ju Bai 5b5ab1bfa1 memory: emif: check the pointer temp in get_device_details()
The pointer temp is allocated by devm_kzalloc(), so it should be
checked for error handling.

Fixes: 7ec944538d ("memory: emif: add basic infrastructure for EMIF driver")
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Link: https://lore.kernel.org/r/20220225132552.27894-1-baijiaju1990@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-03-04 09:08:27 +01:00
Jiasheng Jiang fd7bd80b46 memory: emif: Add check for setup_interrupts
As the potential failure of the devm_request_threaded_irq(),
it should be better to check the return value of the
setup_interrupts() and return error if fails.

Fixes: 68b4aee35d ("memory: emif: add interrupt and temperature handling")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20220224025444.3256530-1-jiasheng@iscas.ac.cn
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-03-04 09:07:42 +01:00
Arnd Bergmann 4d558d4d88 Qualcomm driver updates for v5.18
This refactors the Qualcomm mdt file loader, to partially decouple it
 from the SCM peripheral-authentication-service. This is needed as newer
 platforms, such as the Qualcomm SM8450, require the metadata to remain
 accessible to TrustZone during a longer time. This is followed by the
 introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).
 
 It changes the way hardware version differences are handled in the LLCC
 driver and introduces support for Qualcomm SM8450. While updating the dt
 binding for LLCC it also introduces the missing SM8350 compatible.
 
 The ocmem and aoss drivers gains missing put_device() calls and rpmpd
 gains a missing check for kcalloc() failure.
 
 The SPM driver is updated to avoid instantiating the SPM cpuidle devices
 if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
 operates in 32-bit mode without PSCI.
 
 The RPM power-domain driver gains MSM8226 support.
 
 Lastly the socinfo driver gains knowledge about a few new SoCs and
 PMICs.
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Merge tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.18

This refactors the Qualcomm mdt file loader, to partially decouple it
from the SCM peripheral-authentication-service. This is needed as newer
platforms, such as the Qualcomm SM8450, require the metadata to remain
accessible to TrustZone during a longer time. This is followed by the
introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).

It changes the way hardware version differences are handled in the LLCC
driver and introduces support for Qualcomm SM8450. While updating the dt
binding for LLCC it also introduces the missing SM8350 compatible.

The ocmem and aoss drivers gains missing put_device() calls and rpmpd
gains a missing check for kcalloc() failure.

The SPM driver is updated to avoid instantiating the SPM cpuidle devices
if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
operates in 32-bit mode without PSCI.

The RPM power-domain driver gains MSM8226 support.

Lastly the socinfo driver gains knowledge about a few new SoCs and
PMICs.

* tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (37 commits)
  soc: qcom: rpmpd: Add MSM8226 support
  dt-bindings: power: rpmpd: Add MSM8226 to rpmpd binding
  soc: qcom: mdt_loader: Fix split-firmware condition
  dt-bindings: arm: msm: Add LLCC compatible for SM8450
  dt-bindings: arm: msm: Add LLCC compatible for SM8350
  soc: qcom: llcc: Add configuration data for SM8450 SoC
  soc: qcom: llcc: Update register offsets for newer LLCC HW
  soc: qcom: llcc: Add missing llcc configuration data
  soc: qcom: llcc: Add write-cache cacheable support
  soc: qcom: llcc: Update the logic for version info extraction
  soc: qcom: llcc: Add support for 16 ways of allocation
  soc: qcom: socinfo: Add some more PMICs and SoCs
  firmware: qcom: scm: Add support for MC boot address API
  firmware: qcom: scm: Drop cpumask parameter from set_boot_addr()
  firmware: qcom: scm: Simplify set_cold/warm_boot_addr()
  cpuidle: qcom-spm: Check if any CPU is managed by SPM
  remoteproc: qcom: pas: Add SM8450 remoteproc support
  dt-bindings: remoteproc: qcom: pas: Add SM8450 PAS compatibles
  remoteproc: qcom: pas: Carry PAS metadata context
  soc: qcom: mdt_loader: Extract PAS operations
  ...

Link: https://lore.kernel.org/r/20220301042055.1804859-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 19:24:21 +01:00
Arnd Bergmann 16e769e2ae - add power domains support for mt8195
- disable ACP on mt8192
 
 mt8186:
 - add support for power domains
 - add mmsys and mutex support needed for DRM
 - add reset control based on mmsys subsystem
 - add pmic wrapper
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Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

- add power domains support for mt8195
- disable ACP on mt8192

mt8186:
- add support for power domains
- add mmsys and mutex support needed for DRM
- add reset control based on mmsys subsystem
- add pmic wrapper

* tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  soc: mediatek: pm-domains: Move power status offset to power domain data
  soc: mediatek: pm-domains: Remove unused macro
  soc: mediatek: pm-domains: Add wakeup capacity support in power domain
  dt-bindings: power: Add MT8195 power domains

Link: https://lore.kernel.org/r/16a53482-5a8c-e95e-8cd4-b8304f110987@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 11:09:42 +01:00
Arnd Bergmann 42ba417307 Memory controller drivers for v5.18 - Tegra SoC
1. Correct Tegra20 EMC memory device mask.
 2. Minor improvements.
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Merge tag 'memory-controller-drv-tegra-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18 - Tegra SoC

1. Correct Tegra20 EMC memory device mask.
2. Minor improvements.

* tag 'memory-controller-drv-tegra-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra: Constify struct thermal_cooling_device_ops
  memory: tegra20-emc: Correct memory device mask
  memory: tegra30-emc: Print additional memory info

Link: https://lore.kernel.org/r/20220228164313.52931-3-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 10:59:36 +01:00
Arnd Bergmann 88c7385290 Memory controller drivers for v5.18 - Mediatek SoC
1. Several updates in the MTK SMI bindings.
 2. Add support for MT8186 MTK SMI and improvements in support for MT8195.
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Merge tag 'memory-controller-drv-mediatek-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18 - Mediatek SoC

1. Several updates in the MTK SMI bindings.
2. Add support for MT8186 MTK SMI and improvements in support for MT8195.

* tag 'memory-controller-drv-mediatek-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: mtk-smi: Enable sleep ctrl safety function for MT8195
  memory: mtk-smi: mt8186: Add smi support
  memory: mtk-smi: Add sleep ctrl function
  memory: mtk-smi: handle positive return value for clk_bulk_prepare_enable
  dt-bindings: memory: mediatek: Add mt8186 support
  dt-bindings: memory: mtk-smi: Correct minItems to 2 for the gals clocks
  dt-bindings: memory: mtk-smi: No need mediatek,larb-id for mt8167
  dt-bindings: memory: mtk-smi: Rename clock to clocks

Link: https://lore.kernel.org/r/20220228164313.52931-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 10:52:27 +01:00
Arnd Bergmann b903f9c55e Memory controller drivers for v5.18
1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
    Tegra30.
 2. Convert Freescale/NXP IFC bindings to dtschema.
 3. Convert LPDDR bindings to dtschema.
 4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
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Merge tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18

1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
   Tegra30.
2. Convert Freescale/NXP IFC bindings to dtschema.
3. Convert LPDDR bindings to dtschema.
4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
   bindings.

* tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: Update of_memory lpddr2 revision-id binding
  dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
  memory: of: parse max-freq property
  dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address
  dt-bindings: memory: lpddr3: deprecate manufacturer ID
  dt-bindings: memory: lpddr3: adjust IO width to spec
  dt-bindings: memory: lpddr3: convert to dtschema
  dt-bindings: memory: lpddr3-timings: convert to dtschema
  dt-bindings: memory: lpddr2-timings: convert to dtschema
  memory: brcmstb_dpfe: fix typo in a comment
  memory: fsl_ifc: populate child devices without relying on simple-bus
  dt-bindings: memory: fsl: convert ifc binding to yaml schema
  memory: mtk-smi: Use ARRAY_SIZE to define MTK_SMI_CLK_NR_MAX

Link: https://lore.kernel.org/r/20220228164313.52931-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 10:47:14 +01:00
Rex-BC Chen eb1b02bef5 dt-bindings: arm: mediatek: mmsys: add support for MT8186
Add "mediatek,mt8186-mmsys" to binding document.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220301080105.31323-2-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 09:26:56 +01:00
Johnson Wang a319fbfd3f dt-bindings: mediatek: add compatible for MT8186 pwrap
This adds dt-binding documentation of pwrap for Mediatek MT8186
SoCs Platform.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Link: https://lore.kernel.org/r/20220207083034.15327-3-johnson.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 08:51:23 +01:00
Johnson Wang 83a7175cbe soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
MT8186 are highly integrated SoC and use PMIC_MT6366 for
power management. This patch adds pwrap master driver to
access PMIC_MT6366.

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 08:51:23 +01:00
Rex-BC Chen 831785f0e5 soc: mediatek: mmsys: add mmsys reset control for MT8186
Add mmsys reset control register 0x160 for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220217082626.15728-3-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 08:34:47 +01:00
Alyssa Rosenzweig dcfd519256 soc: mediatek: mtk-infracfg: Disable ACP on MT8192
MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.

Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5

Note this change is required for both Panfrost and the legacy kernel
driver.

Co-developed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Nick Fan <Nick.Fan@mediatek.com>
Cc: Nicolas Boichat <drinkcat@chromium.org>
Cc: Chen-Yu Tsai <wenst@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 08:21:28 +01:00
Arnd Bergmann 254a1864e4 TI Driver updates for v5.18
* Fixups for k3-ringacc, smartreflex, tisci, wkup_m3_ipc
 * Device detection for am62x.
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Merge tag 'ti-driver-soc-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers

TI Driver updates for v5.18

* Fixups for k3-ringacc, smartreflex, tisci, wkup_m3_ipc
* Device detection for am62x.

* tag 'ti-driver-soc-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  soc: ti: k3-socinfo: Add AM62x JTAG ID
  soc: ti: wkup_m3_ipc: Fix IRQ check in wkup_m3_ipc_probe
  firmware: ti_sci: inproper error handling of ti_sci_probe
  firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined
  soc: ti: smartreflex: Use platform_get_irq_optional() to get the interrupt
  soc: ti: k3-ringacc: Use devm_bitmap_zalloc() when applicable

Link: https://lore.kernel.org/r/20220228120655.wobd72acngl2bz6k@ecard
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-28 13:38:51 +01:00
Arnd Bergmann 345932db14 soc/tegra: Changes for v5.18-rc1
This contains the final bit to enable advanced power management on
 Tegra20 and Tegra30. It also contains some cleanups and wake event
 support on Tegra234.
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Merge tag 'tegra-for-5.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.18-rc1

This contains the final bit to enable advanced power management on
Tegra20 and Tegra30. It also contains some cleanups and wake event
support on Tegra234.

* tag 'tegra-for-5.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: bpmp: cleanup double word in comment
  soc/tegra: pmc: Add Tegra234 wake events
  soc/tegra: fuse: Explicitly cast to/from __iomem
  soc/tegra: fuse: Update nvmem cell list
  soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30

Link: https://lore.kernel.org/r/20220225164741.1064416-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-28 13:37:07 +01:00
Vignesh Raghavendra c65d68e7e9 soc: ti: k3-socinfo: Add AM62x JTAG ID
Add JTAG ID entry to help identify AM62x SoC in kernel.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220225120239.1303821-2-vigneshr@ti.com
2022-02-28 05:35:19 -06:00
Yongqiang Niu 15f1768365 soc: mediatek: add MTK mutex support for MT8186
Add MTK mutex support for MT8186 SoC.
We need MTK mutex to control timing of display modules and there
are two display pipelines for MT8186 including internal and external
display.

MTK mutex for internal display:
- Timing source: DSI
- Control modules: OVL0/RDMA0/COLOR0/CCORR/AAL0/GAMMA/POSTMASK0/DITHER

MTK mutex for external display:
- Timing source : DPI
- Control modules: OVL_2L0/RDMA1

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:19:24 +01:00
Yongqiang Niu 5f9b5b757e soc: mediatek: mmsys: add mt8186 mmsys routing table
Add new routing table for MT8186.
In MT8186, there are two routing pipelines for internal and external
display.

Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->
		  DITHER->DSI0
External display: OVL_2L0->RDMA1->DPI0

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:18:39 +01:00
Chun-Jie Chen 88590cbc17 soc: mediatek: pm-domains: Add support for mt8186
Add power domain control data in mt8186.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:11 +01:00
Chun-Jie Chen c8a006896f dt-bindings: power: Add MT8186 power domains
Add power domains dt-bindings for MT8186.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220215104917.5726-2-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:11 +01:00
Chun-Jie Chen 342479c86d soc: mediatek: pm-domains: Add support for mt8195
Add domain control data including bus protection data size
change due to more protection steps in mt8195.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:04 +01:00
Chun-Jie Chen db2ca8608a soc: mediatek: pm-domains: Move power status offset to power domain data
MT8195 has more than 32 power domains so it needs
two set of pwr_sta and pwr_sta2nd registers,
so move the register offset from soc data into power domain data.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:04 +01:00
Chun-Jie Chen dcbf6831a5 soc: mediatek: pm-domains: Remove unused macro
Due to clk resource data will be allocated dynamically by
searching parent count of clk in power domain node, so remove
the unused marco MAX_SUBSYS_CLKS for static allocation.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-4-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:03 +01:00
Chun-Jie Chen ac0ca39554 soc: mediatek: pm-domains: Add wakeup capacity support in power domain
Due to some power domain needs to keep on for wakeup in system suspend,
so add GENPD_FLAG_ACTIVE_WAKEUP support in Mediatek power domain driver.

Fixes: 59b644b01c ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:03 +01:00
Chun-Jie Chen 73c022e129 dt-bindings: power: Add MT8195 power domains
Add power domains dt-bindings for MT8195.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-2-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:03 +01:00
Arnd Bergmann ab930ecfce Samsung clock controller changes for v5.18
Add support for Tesla FSD SoC clock controller within Samsung Exynos SoC
 clock controller drivers.  The Tesla FSD's clock controller is similar
 to Samsung Exynos one, so entire driver structure can be re-used.
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Merge tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers

Samsung clock controller changes for v5.18

Add support for Tesla FSD SoC clock controller within Samsung Exynos SoC
clock controller drivers.  The Tesla FSD's clock controller is similar
to Samsung Exynos one, so entire driver structure can be re-used.

* tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: fix missing Tesla FSD dependency on Exynos
  clk: samsung: fsd: Add cam_csi block clock information
  clk: samsung: fsd: Add cmu_mfc block clock information
  clk: samsung: fsd: Add cmu_imem block clock information
  clk: samsung: fsd: Add cmu_fsys1 clock information
  clk: samsung: fsd: Add cmu_fsys0 clock information
  clk: samsung: fsd: Add cmu_peric block clock information
  clk: samsung: fsd: Add initial clock support
  dt-bindings: clock: Document FSD CMU bindings
  dt-bindings: clock: Add bindings definitions for FSD CMU blocks

Link: https://lore.kernel.org/r/20220204154112.133723-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:14:16 +01:00
Arnd Bergmann b610c55bdf Arm SCMI firmware interface updates for v5.18
Few main additions include:
 - Support for OPTEE based SCMI transport to enable using SCMI service
   provided by OPTEE on some platforms
 - Support for atomic SCMI transports which enables few SCMI transactions
   to be completed in atomic context. This involves other refactoring work
   associated with it. It also marks SMC and OPTEE as atomic transport as
   the commands are completed once the return.
 - Support for polling mode in SCMI VirtIO transport in order to support
   atomic operations
 - Support for atomic clock operations based on availability of atomic
   capability in the underlying SCMI transport
 
 Other changes involves some trace and log enhancements and miscellaneous
 bug fixes.
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Merge tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers

Arm SCMI firmware interface updates for v5.18

Few main additions include:
- Support for OPTEE based SCMI transport to enable using SCMI service
  provided by OPTEE on some platforms
- Support for atomic SCMI transports which enables few SCMI transactions
  to be completed in atomic context. This involves other refactoring work
  associated with it. It also marks SMC and OPTEE as atomic transport as
  the commands are completed once the return.
- Support for polling mode in SCMI VirtIO transport in order to support
  atomic operations
- Support for atomic clock operations based on availability of atomic
  capability in the underlying SCMI transport

Other changes involves some trace and log enhancements and miscellaneous
bug fixes.

* tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (28 commits)
  clk: scmi: Support atomic clock enable/disable API
  firmware: arm_scmi: Add support for clock_enable_latency
  firmware: arm_scmi: Add atomic support to clock protocol
  firmware: arm_scmi: Support optional system wide atomic-threshold-us
  dt-bindings: firmware: arm,scmi: Add atomic-threshold-us optional property
  firmware: arm_scmi: Add atomic mode support to virtio transport
  firmware: arm_scmi: Review virtio free_list handling
  firmware: arm_scmi: Add a virtio channel refcount
  firmware: arm_scmi: Disable ftrace for Clang Thumb2 builds
  firmware: arm_scmi: Add new parameter to mark_txdone
  firmware: arm_scmi: Add atomic mode support to smc transport
  firmware: arm_scmi: Add support for atomic transports
  firmware: arm_scmi: Make optee support sync_cmds_completed_on_ret
  firmware: arm_scmi: Make smc support sync_cmds_completed_on_ret
  firmware: arm_scmi: Add sync_cmds_completed_on_ret transport flag
  firmware: arm_scmi: Make smc transport use common completions
  firmware: arm_scmi: Add configurable polling mode for transports
  firmware: arm_scmi: Use new trace event scmi_xfer_response_wait
  include: trace: Add new scmi_xfer_response_wait event
  firmware: arm_scmi: Refactor message response path
  ...

Link: https://lore.kernel.org/r/20220222201742.3338589-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:05:31 +01:00
Arnd Bergmann c8812c2a08 i.MX drivers update for 5.18:
- Drop LS1021A device check from soc-imx driver as it's unneeded since
   commit commit 4ebd29f916 ("soc: imx: Register SoC device only on
   i.MX boards").
 - Add support for power domains provided by the VPU blk-ctrl on the
   i.MX8MQ.
 - Add resource owner management API which will be used to check whether
   M4 is under control of Linux.
 - Add VPU MU resources support into SCU power domain driver.
 - Support DT overlay for WEIM bus driver with OF reconfiguration
   notifier handler.
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Merge tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers

i.MX drivers update for 5.18:

- Drop LS1021A device check from soc-imx driver as it's unneeded since
  commit commit 4ebd29f916 ("soc: imx: Register SoC device only on
  i.MX boards").
- Add support for power domains provided by the VPU blk-ctrl on the
  i.MX8MQ.
- Add resource owner management API which will be used to check whether
  M4 is under control of Linux.
- Add VPU MU resources support into SCU power domain driver.
- Support DT overlay for WEIM bus driver with OF reconfiguration
  notifier handler.

* tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  bus: imx-weim: add DT overlay support for WEIM bus
  firmware: imx: scu-pd: imx8q: add vpu mu resources
  firmware: imx: add get resource owner api
  soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
  dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  soc: imx: Remove Layerscape check

Link: https://lore.kernel.org/r/20220222075226.160187-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:05:21 +01:00
Arnd Bergmann 25b67f373b TEE shared memory cleanup for v5.18
- The TEE shared memory pool based on two pools is replaced with a single
   somewhat more capable pool.
 - Replaces tee_shm_alloc() and tee_shm_register() with new functions
   easier to use and maintain.  The TEE subsystem and the TEE drivers are
   updated to use the new functions instead.
 - The TEE based Trusted keys routines are updated to use the new
   simplified functions above.
 - The OP-TEE based rng driver is updated to use the new simplified
   functions above.
 - The TEE_SHM-flags are refactored to better match their usage
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Merge tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers

TEE shared memory cleanup for v5.18

- The TEE shared memory pool based on two pools is replaced with a single
  somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
  easier to use and maintain.  The TEE subsystem and the TEE drivers are
  updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
  simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
  functions above.
- The TEE_SHM-flags are refactored to better match their usage

* tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
  tee: refactor TEE_SHM_* flags
  tee: replace tee_shm_register()
  KEYS: trusted: tee: use tee_shm_register_kernel_buf()
  tee: add tee_shm_register_{user,kernel}_buf()
  optee: add optee_pool_op_free_helper()
  tee: replace tee_shm_alloc()
  tee: simplify shm pool handling
  tee: add tee_shm_alloc_user_buf()
  tee: remove unused tee_shm_pool_alloc_res_mem()
  hwrng: optee-rng: use tee_shm_alloc_kernel_buf()
  optee: use driver internal tee_context for some rpc

Link: https://lore.kernel.org/r/20220218184802.GA968155@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:05:11 +01:00
Arnd Bergmann bc5ede20b8 Small simplification in AMDTE driver
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Merge tag 'amdtee-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers

Small simplification in AMDTE driver

* tag 'amdtee-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
  tee: amdtee: Make use of the helper macro LIST_HEAD()

Link: https://lore.kernel.org/r/20220218175632.GA926082@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:05:01 +01:00
Arnd Bergmann f289f1d8a4 Renesas driver updates for v5.18 (take two)
- RZ/G2L and RZ/V2L need PM and PM_GENERIC_DOMAINS,
   - Introduce ARCH_RZG2L family for RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L
     SoCs.
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Merge tag 'renesas-drivers-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.18 (take two)

  - RZ/G2L and RZ/V2L need PM and PM_GENERIC_DOMAINS,
  - Introduce ARCH_RZG2L family for RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L
    SoCs.

* tag 'renesas-drivers-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
  soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs

Link: https://lore.kernel.org/r/cover.1645784470.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:04:50 +01:00
Arnd Bergmann 15cc8d030c Renesas driver updates for v5.18
- Initial support for the new RZ/V2L SoC,
   - RZ/G2L product revision support.
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Merge tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.18

  - Initial support for the new RZ/V2L SoC,
  - RZ/G2L product revision support.

* tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: Add support for reading product revision for RZ/G2L family
  soc: renesas: Identify RZ/V2L SoC

Link: https://lore.kernel.org/r/cover.1644587208.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25 17:04:24 +01:00
Tom Rix fcfaff508b soc/tegra: bpmp: cleanup double word in comment
Remove the second 'or'.

Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25 14:10:09 +01:00
kartik 194217df81 soc/tegra: pmc: Add Tegra234 wake events
Enable the Tegra RTC alarm and power key wake-ups for Tegra234

Signed-off-by: kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25 14:08:46 +01:00
Julius Werner a06bf59d07 memory: Update of_memory lpddr2 revision-id binding
This patch updates the code parsing the "jedec,lpddr2" device tree
binding to use the new `revision-id` property instead of the deprecated
`revision-id1` and `revision-id2` properties if available.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Link: https://lore.kernel.org/r/20220224003421.3440124-3-jwerner@chromium.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-02-25 13:36:49 +01:00
Julius Werner 80ce91730d dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
Commit 3539a2c6c6 ("dt-bindings: memory: lpddr2: Add revision-id
properties") added the properties `revision-id1` and `revision-id2` to
the "jedec,lpddr2" binding. The "jedec,lpddr3" binding already had a
single array property `revision-id` for the same purpose. For
consistency between related memory types, this patch deprecates the
LPDDR2 properties and instead adds a property in the same style as for
LPDDR3 to that binding.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220224003421.3440124-2-jwerner@chromium.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-02-25 13:36:37 +01:00
Conor Dooley d0054a470c soc: add microchip polarfire soc system controller
This driver provides an interface for other drivers to access the
functions of the system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220217101349.2374873-2-conor.dooley@microchip.com
2022-02-25 12:50:59 +01:00
Claudiu Beznea f8e0f301c4 ARM: at91: Kconfig: select PM_OPP
Select PM_OPP. This is requested for CPUFreq driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-6-claudiu.beznea@microchip.com
2022-02-25 12:36:26 +01:00
Claudiu Beznea 9584e7263e ARM: at91: PM: add cpu idle support for sama7g5
Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use automatic self-refresh option of DDR controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-5-claudiu.beznea@microchip.com
2022-02-25 12:36:25 +01:00
Claudiu Beznea 9a0775c9cd ARM: at91: ddr: fix typo to align with datasheet naming
Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet
naming.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
2022-02-25 12:36:25 +01:00
Claudiu Beznea 55614e682a ARM: at91: ddr: align macro definitions
Align all macro definitions.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-3-claudiu.beznea@microchip.com
2022-02-25 12:36:25 +01:00
Claudiu Beznea dc3005703f ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency
Remove CONFIG_SOC_SAMA7 dependency to avoid having #ifdef preprocessor
directives in driver code (arch/arm/mach-at91/pm.c). This prepares the
code for next commits.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-2-claudiu.beznea@microchip.com
2022-02-25 12:36:25 +01:00