Add output-enable generic pin configuration property.
This properties allows enabling/disabling pin's output capabilities
without actually driving any value on the line.
Acked-by: Rob Herring <robh@kernel.org>
[Added inline elaborations on buffer enabling/disabling]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.
Add a compatible string for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W,
- Add support for RZ/G1M and RZ/G1E,
- Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.13
- Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W,
- Add support for RZ/G1M and RZ/G1E,
- Small fixes and cleanups.
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds documentation for the devicetree bindings of the
pinctrl-ingenic driver, which handles pin configuration and pin
muxing of the Ingenic SoCs currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It adds device tree bindings for ZTE pin controller found on ZX2967xx
family SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This reverts commit 8c58f1a7a4.
It turns out that applying these generic properties was
premature: the properties used in the driver using this
are of unclear electrical nature and the subject need to
be discussed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
however it doesn't have several automotive specific peripherals. Annotate
all the items that only exist on the R-Car SoCs and only supply the pin
groups/functions existing on a given SoC...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
trivial fix to spelling mistake in documentation
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl
driver.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document the device tree binding for the pin controllers found on the
Armada 37xx SoCs.
Update the binding documention of the xtal clk which is a subnode of this
syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Fixed gpios node]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add bi-directional and output-enable pin configuration properties.
bi-directional allows to specify when a pin shall operate in input and
output mode at the same time. This is particularly useful in platforms
where input and output buffers have to be manually enabled.
output-enable is just syntactic sugar to specify that a pin shall
operate in output mode, ignoring the provided argument.
This pairs with input-enable pin configuration option.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document "pinmux" property as part of generic pin controller
documentation.
Fix 2 minor typos in documentation while at there.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the bindings for the pinmux functions in the
ARTPEC-6 SoC, including bias and drive strength.
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rockchip finally named the SOC as RV1108, so change it.
Also move the compatible list to one compatible per line.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
which is called "Port Controller (CPUs-PORT)" in SoC User Manual.
Add a binding for this pin controller, like the ones in A23/33 and H3.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The compatible for Allwinner H5 pin controller is wrong written as
allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
rather than a "r" one.
Fix this compatible string.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Note, the iomux of following pins are special, need to
be recalculated specially.
- gpio2_b4
- gpio2_b7
- gpio2_c7
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix typos and add the following to the scripts/spelling.txt:
followings||following
While we are here, add a missing colon in the boilerplate in DT binding
documents. The "you SoC" in allwinner,sunxi-pinctrl.txt was fixed as
well.
I reworded "as the followings:" to "as follows:" for
drivers/usb/gadget/udc/renesas_usb3.c.
Link: http://lkml.kernel.org/r/1481573103-11329-32-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 SoC.
H5 introduced some more pin functions (e.g. three more groups of TS
pins, and one more groups of SIM pins) than H3.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add missing compatible id for Exynos3250 SoC to device tree docs.
Exynos pin control driver supports it since commit d97f5b9804
("pinctrl: exynos: Add driver data for Exynos3250").
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SoC family such as DRA7 family of processors have, in addition
to the regular muxing of pins (as done by pinctrl-single), a separate
hardware module called IODelay which is also expected to be configured.
The "IODelay" module has it's own register space that is independent
of the control module and the padconf register area.
With recent changes to the pinctrl framework, we can now support
this hardware with a reasonably minimal driver by using #pinctrl-cells,
GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS.
It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay reconfiguration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do as little of muxing as absolutely necessary
without I/O isolation (which can only be done in initial stages of
bootloader).
NOTE: with the system wide I/O isolation scheme present in DRA7 SoC
family, it is not reasonable to do stop all I/O operations for every
such pad configuration scheme. So, we will let it glitch when used in
this mode.
Even with the above limitation, certain functionality such as MMC has
mandatory need for IODelay reconfiguration requirements, depending on
speed of transfer. In these cases, with careful examination of usecase
involved, the expected glitch can be controlled such that it does not
impact functionality.
In short, IODelay module support as a padconf driver being introduced
here is not expected to do SoC wide I/O Isolation and is meant for
a limited subset of IODelay configuration requirements that need to
be dynamic and whose glitchy behavior will not cause functionality
failure for that interface.
IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared
to 0x0 at all times, even when configuring Manual IO Timing Modes.
This is done by eliminating the LOCK_BIT=1 setting from Step
of the Manual IO timing Mode configuration procedure. This option
leaves the CFG_* registers unprotected from unintended writes to the
CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured.
This approach is taken to allow for a generic driver to exist in kernel
world that has to be used carefully in required usecases.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[tony@atomide.com: updated to use generic pinctrl functions, added
binding documentation, updated comments]
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On Marvell mv88f6180 mpp pins range from 0 to 19 as well as from 35 to 44.
This is already fixed in commit: 9573e79230
This is the documentation change for above commit.
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The patch introducing the g5 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms and the AST2500 evaluation board.
Now, update the bindings document to reflect the complete functionality
and implement the necessary pin configuration tables in the driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The patch introducing the g4 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms. Now, update the bindings document
to reflect the complete functionality and implement the necessary pin
configuration tables in the driver.
Cc: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The System Control Unit IP block in the Aspeed SoCs is typically where
the pinmux configuration is found, but not always. A number of pins
depend on state in one of LPC Host Control (LHC) or SoC Display
Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
means to adjust these as necessary.
We use syscon to cast a regmap over the GFX and LPC blocks, which is
used as an arbitration layer between the relevant driver and the pinctrl
subsystem. The regmaps are then exposed to the SoC-specific pinctrl
drivers by phandles in the devicetree, and are selected during a mux
request by querying a new 'ip' member in struct aspeed_sig_desc.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reference the SoC-specific compatible string in the examples as
required.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where things
come together.
We get a DT descriptions for a couple of new SoCs, all of them variants
of other chips we already support, and usually coming with a new
evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers
or industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on
Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it into
products and have served their purpose in the kernel as a template
for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree
Conflicts:
arch/arm/boot/dts/r8a*.dtsi: a node was added
the clk tree, keep both sides and watch out for git
dropping the required '};' at the end of each side.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where
things come together.
We get a DT descriptions for a couple of new SoCs, all of them
variants of other chips we already support, and usually coming with a
new evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers or
industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it
into products and have served their purpose in the kernel as a
template for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)
arm: dts: zynq: Add MicroZed board support
ARM: dts: da850: enable high speed for mmc
ARM: dts: da850: Add node for pullup/pulldown pinconf
ARM: dts: da850: enable memctrl and mstpri nodes per board
ARM: dts: da850-lcdk: Add ethernet0 alias to DT
ARM: dts: artpec: add pcie support
ARM: dts: add support for Turris Omnia
devicetree: Add vendor prefix for CZ.NIC
ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
ARM: dts: berlin2q-marvell-dmp: fix regulators' name
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM: dts: r8a7794: Add device node for PRR
ARM: dts: r8a7793: Add device node for PRR
ARM: dts: r8a7792: Add device node for PRR
ARM: dts: r8a7791: Add device node for PRR
ARM: dts: r8a7790: Add device node for PRR
ARM: dts: r8a7779: Add device node for PRR
ARM: dts: r8a73a4: Add device node for PRR
ARM: dts: sk-rzg1e: add Ether support
ARM: dts: sk-rzg1e: initial device tree
...
No core changes this time. Mainly gradual improvement and
feature growth in the drivers.
New drivers:
- New driver for TI DA850/OMAP-L138/AM18XX pinconf
- The SX150x was moved over from the GPIO subsystem and
reimagined as a pin control driver with GPIO support
in a joint effort by three independent users of this
hardware. The result was amazingly good!
- New subdriver for the Oxnas OX820
Improvements:
- The sunxi driver now supports the generic pin control
bindings rather than the sunxi-specific. Add debouncing
support to the driver.
- Simplifications in pinctrl-single adding a generic parser.
- Two downstream fixes and move the Raspberry Pi BCM2835 over
to use the generic GPIOLIB_IRQCHIP.
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Merge tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl updates from Linus Walleij:
"Bulk pin control changes for the v4.10 kernel cycle:
No core changes this time. Mainly gradual improvement and
feature growth in the drivers.
New drivers:
- New driver for TI DA850/OMAP-L138/AM18XX pinconf
- The SX150x was moved over from the GPIO subsystem and reimagined as
a pin control driver with GPIO support in a joint effort by three
independent users of this hardware. The result was amazingly good!
- New subdriver for the Oxnas OX820
Improvements:
- The sunxi driver now supports the generic pin control bindings
rather than the sunxi-specific. Add debouncing support to the
driver.
- Simplifications in pinctrl-single adding a generic parser.
- Two downstream fixes and move the Raspberry Pi BCM2835 over to use
the generic GPIOLIB_IRQCHIP"
* tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (92 commits)
pinctrl: sx150x: use new nested IRQ infrastructure
pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505
pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'
pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]
pinctrl: mt8173: set GPIO16 to usb iddig mode
pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP
pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf
devicetree: bindings: pinctrl: Add binding for ti,da850-pupd
Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition
pinctrl: intel: set default handler to be handle_bad_irq()
pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507
pinctrl: sx150x: sort chips by part number
pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)
pinctrl: imx: fix imx_pinctrl_desc initialization
pinctrl: sx150x: support setting multiple pins at once
pinctrl: sx150x: various spelling fixes and some white-space cleanup
pinctrl: mediatek: use builtin_platform_driver
pinctrl: stm32: use builtin_platform_driver
pinctrl: sunxi: Testing the wrong variable
pinctrl: nomadik: split up and comments MC0 pins
...
Core changes:
- Simplify threaded interrupt handling: instead of passing
numbed parameters to gpiochip_irqchip_add_chained() we
create a new call: gpiochip_irqchip_add_nested() so the two
types are clearly semantically different. Also make sure
that all nested chips call gpiochip_set_nested_irqchip()
which is necessary for IRQ resend to work properly if
it happens.
- Return error on seek operations for the chardev.
- Clamp values set as part of gpio[d]_direction_output() so
that anything != 0 will be send down to the driver as "1"
not the value passed in.
- ACPI can now support naming of GPIO lines, hogs and holes
in the GPIO lists.
New drivers:
- The SX150x driver was deemed unfit for the GPIO subsystem
and was moved over to a combined GPIO+pinctrl driver in the
pinctrl subsystem.
New features:
- Various cleanups to various drivers.
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Merge tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Luinus Walleij:
"Bulk GPIO changes for the v4.10 kernel cycle:
Core changes:
- Simplify threaded interrupt handling: instead of passing numbed
parameters to gpiochip_irqchip_add_chained() we create a new call:
gpiochip_irqchip_add_nested() so the two types are clearly
semantically different. Also make sure that all nested chips call
gpiochip_set_nested_irqchip() which is necessary for IRQ resend to
work properly if it happens.
- Return error on seek operations for the chardev.
- Clamp values set as part of gpio[d]_direction_output() so that
anything != 0 will be send down to the driver as "1" not the value
passed in.
- ACPI can now support naming of GPIO lines, hogs and holes in the
GPIO lists.
New drivers:
- The SX150x driver was deemed unfit for the GPIO subsystem and was
moved over to a combined GPIO+pinctrl driver in the pinctrl
subsystem.
New features:
- Various cleanups to various drivers"
* tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (49 commits)
gpio: merrifield: Implement gpio_get_direction callback
gpio: merrifield: Add support for hardware debouncer
gpio: chardev: Return error for seek operations
gpio: arizona: Tidy up probe error path
gpio: arizona: Remove pointless set of platform drvdata
gpio: pl061: delete platform data handling
gpio: pl061: move platform data into driver
gpio: pl061: rename variable from chip to pl061
gpio: pl061: rename state container struct
gpio: pl061: use local state for parent IRQ storage
gpio: set explicit nesting on drivers
gpio: simplify adding threaded interrupts
gpio: vf610: use builtin_platform_driver
gpio: axp209: use correct register for GPIO input status
gpio: stmpe: fix interrupt handling bug
gpio: em: depnd on ARCH_SHMOBILE
gpio: zx: depend on ARCH_ZX
gpio: x86: update config dependencies for x86 specific hardware
gpio: mb86s7x: use builtin_platform_driver
gpio: etraxfs: use builtin_platform_driver
...
Device-tree bindings for TI DA850/OMAP-L138/AM18XX pullup/pulldown
pinconf controller.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO7 is configured in POWERHOLD mode which has higher priority
over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON
bit is turned off. This property enables driver to over ride the
POWERHOLD value to GPIO7 so as to turn off the PMIC in power off
scenarios.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
us to use generic parser later on. Note that the driver supports
handling the legacy binding also with no #pinctrl-cells so these
changes can be queued separately from the driver changes.
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Merge tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Add #pinctrl-cells for pinctrl-single using dts files. This allows
us to use generic parser later on. Note that the driver supports
handling the legacy binding also with no #pinctrl-cells so these
changes can be queued separately from the driver changes.
* tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Add #pinctrl-cells for pinctrl-single instances
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the dt-binding documentation for rk1108 pinctrl
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.
However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.
Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.
Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Initial pinctrl driver for QCOM msm8994 platforms.
In order to continue the initial board support for QCOM msm8994/msm8992
presented in patches from Jeremy McNicoll <jeremymc@redhat.com>, let's put
a proper pinctrl driver in place.
Currently, the DT for these platforms uses the msm8x74 pinctrl driver to
enable basic UART. Beyond the first few pins the rest are different enough
to justify it's own driver.
Note: This driver is also used by QCOM's msm8992 platform as it's TLM block
is the same.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
- Data was then adjusted per QCOM MSM8994v2 documentation for Top Level
Multiplexing
- Bindings documentation was based on qcom,msm8996-pinctrl.txt by
Joonwoo Park <joonwoop@codeaurora.org> and then modified for msm8994
content
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the Amlogic Meson GXL SoC, this is a partially complete
definition only based on the Amlogic Vendor tree.
This definition differs a lot from the GXBB and needs a separate entry.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
stm32 pinctrl driver could be probed even if no interrupt controller
is defined to manage gpio irqs. Entries related to gpio irq management
are moved to optional.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for pin output control through the pinctrl config:
- support enabling/disabling output on a given pin
- support output level setting (high or low)
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the I2C sx150x GPIO expander driver uses platform_data to manage
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get/set pin configurations from DT or debugfs.
The pinctrl driver is functionnally equivalent as the gpio-only driver
and can use DT for pinconf. The platform_data confirmation is dropped.
This patchset removed the gpio-only driver and selects the Pinctrl driver
config instead. This patchset also migrates the gpio dt-bindings to pinctrl
and add the pinctrl optional properties.
The driver was tested with a SX1509 device on a BeagleBone black with
interrupt support and on an X86_64 machine over an I2C to USB converter.
This is a fixed version that builds and runs on non-OF platforms and on
arm based OF. The GPIO version is removed and the bindings are also moved
to the pinctrl bindings.
Changes since v2
- rebased on v4.9-rc1
- removed MODULE_DEVICE_TABLE as in upstream bb411e771b
("gpio: sx150x: fix implicit assumption module.h is present")
Changes since v1
- Fix Kconfig descriptions on pinctrl and gpio
- Fix Kconfig dependency
- Remove oscio support for non-789 devices
- correct typo in dt bindings
- remove probe reset for non-789 devices
Changes since RFC
- Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
- No more rely on OF_GPIO config
- Moved and enhanced bindings to pinctrl bindings
- Removed gpio-sx150x.c
- Temporary select PINCTRL_SX150X when GPIO_SX150X
- Temporary mark GPIO_SX150X as deprecated
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Peter Rosin <peda@axentia.se>
Acked-by: Rob Herring <robh@kernel.org>
ested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The generic pin configuration and multiplexing should be preferred now,
even though we still support the old one.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SPI1 function was associated with the wrong pins: The functions that
those pins provide is either an SPI debug or passthrough function
coupled to SPI1. Make the SPI1 mux function configure the relevant pins
and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
that were already defined.
The notation used in the datasheet's multi-function pin table for the SoC is
often creative: in this case the SYS* signals are enabled by a single bit,
which is nothing unusual on its own, but in this case the bit was also
participating in a multi-bit bitfield and therefore represented multiple
functions. This fact was overlooked in the original patch.
Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These are as usual a very large number of mostly boring updates to
enable devices in existing machines, or to fix minor bugs. Notably,
an ongoing treewide effort to fix warnings caused by an update to the
device tree compiler. These are enabled with "make W=1" at the moment
but can hopefully become the default once all issues have been addressed.
No new SoC platform is added this time around (Armada 395 and Orion
mv88f5181 are slight variations of existing ones), but a significant
number of new dts files are added, which I list by platform:
- Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets;
Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E,
Orange Pi Lite, Olimex A33-Olinuxino, and Nano Pi Neo
single-board computers
- ARM Realview: all supported machines (ported from board files)
- Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and
BCM958622hr reference boards for Northstar platform;
Raspberry Pi Zero single-board computer
- Marvell EBU: Netgear WNR854T router (ported from board file);
Armada 395 SoC platform and GP board
Armada 390 DB development board
- NXP i.MX: imx7s Warp7 reference board;
Gateworks Ventana GW553x single-board computer,
Technologic Systems TS-4900 and
Engicam IMX6UL GEA M6UL computer-on-module,
Inverse Path USB armory board
- Qualcomm: LG Nexus 5 Phone
- Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards
- Rockchip: Rockchip RK3288 Fennec reference board;
Firefly RK3288 Reload platform
- ST Microelectronics STi: B2260 (96boards) single-board computer
- TI Davinci: OMAP-L138 LCDK Development kit
- TI OMAP: beagleboard-x15 rev B1 single-board computer
Conflicts: vendor-prefixes.txt has conflicting additions, keep all of
them in alphabetical order.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are as usual a very large number of mostly boring updates to
enable devices in existing machines, or to fix minor bugs. Notably, an
ongoing treewide effort to fix warnings caused by an update to the
device tree compiler. These are enabled with "make W=1" at the moment
but can hopefully become the default once all issues have been
addressed.
No new SoC platform is added this time around (Armada 395 and Orion
mv88f5181 are slight variations of existing ones), but a significant
number of new dts files are added, which I list by platform:
- Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets,
Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E, Orange Pi Lite,
Olimex A33-Olinuxino, and Nano Pi Neo single-board computers
- ARM Realview: all supported machines (ported from board files)
- Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and
BCM958622hr reference boards for Northstar platform, Raspberry Pi
Zero single-board computer
- Marvell EBU: Netgear WNR854T router (ported from board file),
Armada 395 SoC platform and GP board Armada 390 DB development
board
- NXP i.MX: imx7s Warp7 reference board, Gateworks Ventana GW553x
single-board computer, Technologic Systems TS-4900 and Engicam
IMX6UL GEA M6UL computer-on-module, Inverse Path USB armory board
- Qualcomm: LG Nexus 5 Phone
- Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards
- Rockchip: Rockchip RK3288 Fennec reference board, Firefly RK3288
Reload platform
- ST Microelectronics STi: B2260 (96boards) single-board computer
- TI Davinci: OMAP-L138 LCDK Development kit
- TI OMAP: beagleboard-x15 rev B1 single-board computer"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (390 commits)
ARM: dts: sony-nsz-gs7: add missing unit name to /memory node
ARM: dts: chromecast: add missing unit name to /memory node
ARM: dts: berlin2q-marvell-dmp: add missing unit name to /memory node
ARM: dts: berlin2: Add missing unit name to /soc node
ARM: dts: berlin2cd: Add missing unit name to /soc node
ARM: dts: berlin2q: Add missing unit name to /soc node
ARM: dts: berlin2: Remove skeleton.dtsi inclusion
ARM: dts: berlin2cd: Remove skeleton.dtsi inclusion
ARM: dts: berlin2q: Remove skeleton.dtsi inclusion
arm: dts: berlin2q: enable all wdt nodes unconditionally
arm: dts: berlin2: enable all wdt nodes unconditionally
ARM: dts: omap5-igep0050.dts: Use tabs for indentation
ARM: dts: Fix igepv5 power button GPIO direction
ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node
ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
ARM: dts: s3c64xx: Use macros for pinctrl configuration
ARM: dts: s3c2416: Use macros for pinctrl configuration
ARM: dts: s5pv210: Use macros for pinctrl configuration
ARM: dts: s3c64xx: Use common macros for pinctrl configuration
...
Driver updates for ARM SoCs, including a couple of newly added drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the
EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.
[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Update examples in Samsung pinctrl dt-bindings with new macros coming
from header file.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl dt doc and removes
references to these obsolete platforms. It also updates
the dt example to the currently supported STiH407
platform.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <robh+dt@kernel.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial support for the Pin Function Controller on the Renesas R-Car
M3-W SoC:
- Basic definitions,
- SCIF (serial) pins, groups and functions,
- SDHI pins, groups and functions.
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Merge tag 'sh-pfc-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Add support for R-Car M3-W
Add initial support for the Pin Function Controller on the Renesas R-Car
M3-W SoC:
- Basic definitions,
- SCIF (serial) pins, groups and functions,
- SDHI pins, groups and functions.
- Bias and DU support for R-Car H3,
- Basic R-Car V2H support,
- Cleanups and fixes.
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Merge tag 'sh-pfc-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.9
- Bias and DU support for R-Car H3,
- Basic R-Car V2H support,
- Cleanups and fixes.
This patch adds initial pinctrl driver to support for the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: rebased on top of renesas-drivers]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch allows to use the second parameter of gpio
specifier, which is used to specify whether the gpio is
active high or low.
Simply remove specific of_xlate callback() and of_gpio_n_cells
and use default one set by of_gpiochip_add() which allows
to use second parameter gpio specifier.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The drivers don't really need to know which PMIC they're for, so
make a generic binding for them. This alleviates us from updating
the drivers every time a new PMIC comes out. It's still
recommended that we update the binding with new PMIC models and
always specify the specific model for the MPPs and gpios before
the generic compatible string in devicetree, but this at least
cuts down on adding more and more compatible strings to the
drivers until we actually need them.
Cc: <devicetree@vger.kernel.org>
Acked-by: "Ivan T. Ivanov" <iivanov.xz@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the PFC support for the R8A7792 SoC including pin groups for some
on-chip devices such as SCIF, INTC, and LBSC...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[geert: s/LSBC/LBSC/]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Merge drm updates from Dave Airlie:
"This is the main drm pull request for 4.8.
I'm down with a cold at the moment so hopefully this isn't in too bad
a state, I finished pulling stuff last week mostly (nouveau fixes just
went in today), so only this message should be influenced by illness.
Apologies to anyone who's major feature I missed :-)
Core:
Lockless GEM BO freeing
Non-blocking atomic work
Documentation changes (rst/sphinx)
Prep for new fencing changes
Simple display helpers
Master/auth changes
Register/unregister rework
Loads of trivial patches/fixes.
New stuff:
ARM Mali display driver (not the 3D chip)
sii902x RGB->HDMI bridge
Panel:
Support for new panels
Improved backlight support
Bridge:
Convert ADV7511 to bridge driver
ADV7533 support
TC358767 (DSI/DPI to eDP) encoder chip support
i915:
BXT support enabled by default
GVT-g infrastructure
GuC command submission and fixes
BXT workarounds
SKL/BKL workarounds
Demidlayering device registration
Thundering herd fixes
Missing pci ids
Atomic updates
amdgpu/radeon:
ATPX improvements for better dGPU power control on PX systems
New power features for CZ/BR/ST
Pipelined BO moves and evictions in TTM
GPU scheduler improvements
GPU reset improvements
Overclocking on dGPUs with amdgpu
Polaris powermanagement enabled
nouveau:
GK20A/GM20B volt and clock improvements.
Initial support for GP100/GP104 GPUs, GP104 will not yet support
acceleration due to NVIDIA having not released firmware for them as of yet.
exynos:
Exynos5433 SoC with IOMMU support.
vc4:
Shader validation for branching
imx-drm:
Atomic mode setting conversion
Reworked DMFC FIFO allocation
External bridge support
analogix-dp:
RK3399 eDP support
Lots of fixes.
rockchip:
Lots of small fixes.
msm:
DT bindings cleanups
Shrinker and madvise support
ASoC HDMI codec support
tegra:
Host1x driver cleanups
SOR reworking for DP support
Runtime PM support
omapdrm:
PLL enhancements
Header refactoring
Gamma table support
arcgpu:
Simulator support
virtio-gpu:
Atomic modesetting fixes.
rcar-du:
Misc fixes.
mediatek:
MT8173 HDMI support
sti:
ASOC HDMI codec support
Minor fixes
fsl-dcu:
Suspend/resume support
Bridge support
amdkfd:
Minor fixes.
etnaviv:
Enable GPU clock gating
hisilicon:
Vblank and other fixes"
* tag 'drm-for-v4.8' of git://people.freedesktop.org/~airlied/linux: (1575 commits)
drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup
drm/nouveau/acpi: fix lockup with PCIe runtime PM
drm/nouveau/acpi: check for function 0x1B before using it
drm/nouveau/acpi: return supported DSM functions
drm/nouveau/acpi: ensure matching ACPI handle and supported functions
drm/nouveau/fbcon: fix font width not divisible by 8
drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events
drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce
drm/amdgpu: add query device id and revision id into system info entry at CGS
drm/amdgpu: add new definition in bif header
drm/amd/powerplay: rename smum header guards
drm/amdgpu: enable UVD context buffer for older HW
drm/amdgpu: fix default UVD context size
drm/amdgpu: fix incorrect type of info_id
drm/amdgpu: make amdgpu_cgs_call_acpi_method as static
drm/amdgpu: comment out unused defaults_staturn_pro static const structure to fix the build
drm/amdgpu: enable UVD VM only on polaris
drm/amdgpu: increase timeout of IB test
drm/amdgpu: add destroy session when generate VCE destroy msg.
drm/amd: fix deadlock of job_list_lock V2
...
Update the iProc GPIO binding document to add new compatible strings
"brcm,iproc-nsp-gpio" and "brcm,iproc-stingray-gpio" to support the
iProc based GPIO controller used in the NSP and Stingray SoCs,
respectively
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the ebi2 and ebi2cs groups to the MSM8660 pin control
documentation document.
Cc: devicetree@vger.kernel.org
Cc: Andy Gross <andy.gross@linaro.org>
Cc: Björn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On Tegra124, Tegra132 and Tegra210 devices the pads used by the Display
Port Auxiliary (DPAUX) channel are multiplexed such that they can also
be used by one of the internal I2C controllers. Note that this is
different from I2C-over-AUX supported by the DPAUX controller. The
register that configures these pads is part of the DPAUX controllers
register set and so a pinctrl driver is being added for the DPAUX device
to share these pads. Add the device-tree binding documentation for the
DPAUX pad controller.
Although there is only one group of pads associated with the DPAUX that
can be multiplexed, the group still needs to be described by the binding.
If the 'groups' property is not present in the binding, then the pads
will not be allocated by the pinctrl core for a client and this would
allow another client to re-configure the same pads that may already be
in-use.
Please note that although the "off" function for the DPAUX pads is not
technically a pin-mux setting but more of a pin-conf setting it is
simpler to expose these as a function so that the user can simply select
either "aux", "i2c" or "off" as the current function/mode.
Update the main DPAUX binding documentation to reference the DPAUX pad
controller binding document and add the 'i2c-bus' subnode. The 'i2c-bus'
subnode is used for populating I2C slaves for the DPAUX device so that
the I2C driver core does not attempt to add the DPAUX pad controller
nodes as I2C slaves.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The msm8974 pinctrl variant has a couple USB HSIC "glue"
registers that let us mux between the pinctrl register settings
or the HSIC core settings for the HSIC pins (gpio 144 and gpio
145). Support this method of operation by adding hsic_data and
hsic_strobe pins that can select between hsic_ctl and gpio
functions. This allows us to toggle the hsic pin configuration
over to the HSIC core at runtime.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Voltage switching support for R-Car H3,
- DRIF pin support for R-Car H3,
- Cleanups and fixes.
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Merge tag 'sh-pfc-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.8
- Voltage switching support for R-Car H3,
- DRIF pin support for R-Car H3,
- Cleanups and fixes.
The PM8058 is found in connection to the APQ8060 on the APQ8060
Dragonboard. Works the same as all others, just add the compatible
string for this variant.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It must be "drive-strength", with a hyphen.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the two new compatibles for the Amlogic Meson GXBB pin controllers.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins
which act as GPIO as well as special function mode.
Add DT binding document to configure pins in function mode as
well as pin configuration parameters.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These warnings
are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
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Merge tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These
warnings are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
* tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (52 commits)
devicetree: Add Creative Technology vendor id
gpio: dt-bindings: add ibm,ppc4xx-gpio binding
of/unittest: Remove unnecessary module.h header inclusion
drivers/of: Fix build warning in populate_node()
drivers/of: Fix depth when unflattening devicetree
of: dynamic: changeset prop-update revert fix
drivers/of: Export of_detach_node()
drivers/of: Return allocated memory from of_fdt_unflatten_tree()
drivers/of: Specify parent node in of_fdt_unflatten_tree()
drivers/of: Rename unflatten_dt_node()
drivers/of: Avoid recursively calling unflatten_dt_node()
drivers/of: Split unflatten_dt_node()
of: include errno.h in of_graph.h
of: document refcount incrementation of of_get_cpu_node()
Documentation: dt: soc: fix spelling mistakes
Documentation: dt: power: fix spelling mistake
Documentation: dt: pinctrl: fix spelling mistake
Documentation: dt: opp: fix spelling mistake
Documentation: dt: net: fix spelling mistakes
Documentation: dt: mtd: fix spelling mistake
...
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable drivers
to use it, saving lots of lines of code all over the place.
New drivers:
- New driver for the Broadcom NS2 SoC.
- New subdriver for the PXA25x SoCs.
- New subdriver for the AMLogic Meson GXBB SoC.
Driver improvements:
- The Intel Baytrail driver now properly supports pin control.
- The Nomadik, Rockchip, Broadcom BCM2835 supports the .get_direction() callback in
the GPIO portions.
- Continued development and stabilization of several SH-PFC
SoC subdrivers: r8a7795, r8a7790, r8a7794 etc.
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Merge tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This kernel cycle was quite calm when it comes to pin control and
there is really just one major change, and that is the introduction of
devm_pinctrl_register() managed resources.
Apart from that linear development, details below.
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable
drivers to use it, saving lots of lines of code all over the place.
New drivers:
- driver for the Broadcom NS2 SoC
- subdriver for the PXA25x SoCs
- subdriver for the AMLogic Meson GXBB SoC
Driver improvements:
- the Intel Baytrail driver now properly supports pin control
- Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction()
callback in the GPIO portions
- continued development and stabilization of several SH-PFC SoC
subdrivers: r8a7795, r8a7790, r8a7794 etc"
* tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits)
Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
pinctrl: meson: Fix eth_tx_en bit index
pinctrl: tegra: avoid parked_reg and parked_bank
pinctrl: tegra: Correctly check the supported configuration
pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
pinctrl: rockchip: fix pull setting error for rk3399
pinctrl: stm32: Implement .pin_config_dbg_show()
pinctrl: nomadik: hide nmk_gpio_get_mode when unused
pinctrl: ns2: rename pinctrl_utils_dt_free_map
pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable
pinctrl: at91: Make at91_gpio_template const
pinctrl: baytrail: fix some error handling in debugfs
pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC
pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged
pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove()
pinctrl: nomadik: implement .get_direction()
pinctrl: nomadik: use BIT() with offsets consequently
pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range
pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration
pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration
...
Driver updates for ARM SoCs, these contain various things that touch
the drivers/ directory but got merged through arm-soc for practical
reasons. For the most part, this is now related to power management
controllers, which have not yet been abstracted into a separate
subsystem, and typically require some code in drivers/soc or arch/arm
to control the power domains.
Another large chunk here is a rework of the NVIDIA Tegra USB3.0
support, which was surprisingly tricky and took a long time to
get done.
Finally, reset controller handling as always gets merged through here
as well.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, these contain various things that touch
the drivers/ directory but got merged through arm-soc for practical
reasons.
For the most part, this is now related to power management
controllers, which have not yet been abstracted into a separate
subsystem, and typically require some code in drivers/soc or arch/arm
to control the power domains.
Another large chunk here is a rework of the NVIDIA Tegra USB3.0
support, which was surprisingly tricky and took a long time to get
done.
Finally, reset controller handling as always gets merged through here
as well"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits)
arm-ccn: Enable building as module
soc/tegra: pmc: Add generic PM domain support
usb: xhci: tegra: Add Tegra210 support
usb: xhci: Add NVIDIA Tegra XUSB controller driver
dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support
dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding
PCI: tegra: Support per-lane PHYs
dt-bindings: pci: tegra: Update for per-lane PHYs
phy: tegra: Add Tegra210 support
phy: Add Tegra XUSB pad controller support
dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding
phy: core: Allow children node to be overridden
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
drivers: firmware: psci: make two helper functions inline
soc: renesas: rcar-sysc: Add support for R-Car H3 power areas
soc: renesas: rcar-sysc: Add support for R-Car E2 power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas
soc: renesas: rcar-sysc: Add support for R-Car H2 power areas
...
This set of patches adds support for the Tegra XUSB pad controller. The
controller provides a set of pads (lanes) that are used for I/O by other
IP blocks within Tegra SoCs (PCIe, SATA and XUSB).
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Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
Merge "phy: tegra: Changes for v4.7-rc1" from Thierry Reding:
This set of patches adds support for the Tegra XUSB pad controller. The
controller provides a set of pads (lanes) that are used for I/O by other
IP blocks within Tegra SoCs (PCIe, SATA and XUSB).
* tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
phy: tegra: Add Tegra210 support
phy: Add Tegra XUSB pad controller support
dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding
phy: core: Allow children node to be overridden
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
set of lanes that are used for PCIe, SATA and USB.
A binding exists for the XUSB pad controller already, but it turned out
not to be flexible enough to describe all aspects of the controller. In
particular, the addition of XUSB support (for SuperSpeed USB) has shown
that the existing binding is no longer suitable. Mark the old binding
as deprecated and link to the new binding.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
A batch of fixes for -rc4, for various platforms. Nothing really
substantial and worth pointing out in particular; small fixes for various
bugs, see shortlog for details.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A batch of fixes for -rc4, for various platforms.
Nothing really substantial and worth pointing out in particular; small
fixes for various bugs, see shortlog for details"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: sa1100: remove references to the defunct handhelds.org
bus: uniphier-system-bus: fix condition of overlap check
ARM: uniphier: drop weird sizeof()
ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type
ARM: OMAP: Correct interrupt type for ARM TWD
ARM: DRA722: Add ID detect for Silicon Rev 2.0
ARM: dts: am43xx: fix edma memcpy channel allocation
ARM: dts: AM43x-epos: Fix clk parent for synctimer
ARM: OMAP2: Fix up interconnect barrier initialization for DRA7
documentation: Fix pinctrl documentation for Meson8 / Meson8b
ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
ARM: mvebu: Correct unit address for linksys
bus: mvebu-mbus: use %pa to print phys_addr_t
arm64: dts: vulcan: Update PCI ranges
ARM: u8500_defconfig: turn on the Synaptics RMI4 driver
ARM: pxa: fix the number of DMA requestor lines
ARM: OMAP2+: hwmod: Fix updating of sysconfig register
ARM: OMAP2+: Use srst_udelay for USB on dm814x
Fix pin controller documentation introducing the new compatibles for
the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we
have now a single specialized pinctrl driver / compatible for each bus
the controller is attached to, instead of one single driver dealing with
all the controllers we have on different buses.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Rob Herring <robh@kernel.org>
Add support for the drive-strengh pin configuration using the generic
pinconf DT bindings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible string
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible
string"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
ARM: dts: artpec: dual-license on artpec6.dtsi
ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
...
Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwinner A64 SoC.
Port A is apparently used for the fixed function DRAM controller, so
the ports start at B here (the manual mentions "n from 1 to 7", so
not starting at 0).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update devicetree documention for lpc1850-scu with the new
nxp,gpio-pin-interrupt property.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
allwinner,sun8i-h3-r-pinctrl was added by
commit ba83a11104 ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl of rk3399 is much different from other's,
especially the 3bits of drive strength.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the commit a526973e02 ("pinctrl: mvebu: Fix mapping of pin
63 (gpo -> gpio)"), the mpp63 is no more declared as a GPO but is a
GPIO. Even if in the datasheet this pin is described as GPO, the
experience of the D-Link DNS-327L board shows that it can be used as a
GPIO.
This commits generated warnings for the board using this pin as gpo, with
this patch the dts are fixed by using the new function (gpio) instead of
the old one.
The binding documentation has also been updated accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Document the devicetree bindings for PINCTRL and GPIO found on Microchip
PIC32 class devices.
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.
Add a driver for this controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens: Add A80 compatible strings to bindings doc; fix pin function
names based on v1.3 datasheet; constify of_device_id table]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl of rk3228 is much the same as rk3288's, but
without pmu.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the driver and binding for pm8994-mpp devices.
Cc: <devicetree@vger.kernel.org>
Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Björn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the binding and driver for pm8994-gpio devices.
Cc: <devicetree@vger.kernel.org>
Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Björn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8996.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
[sboyd@codeaurora.org: Remove duplicate entries and enums]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Björn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the new dedicated "lantiq,<chip>-pinctrl" compatible strings
to the devicetree bindings Documentation, where <chip> is one of "ase",
"danube", "xrx100", "xrx200" or "xrx300" and marks the "lantiq,pinctrl-xway",
"lantiq,pinctrl-ase" and "lantiq,pinctrl-xr9" compatible strings as DEPRECATED.
Signed-off-by: Martin Schiller <mschiller@tdt.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Renamed gpio controller's driver name from cygnus to iproc to make it
more generic so that all iProc based SoCs having the same gpio controller
could use this.
Signed-off-by: Pramod Kumar <pramodku@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add ngpios property to the gpio controller's DT node so that controller
driver extracts total number of in-use gpio lines from DT and removes
dependency on driver.
Signed-off-by: Pramod Kumar <pramodku@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com>
[AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Tested-by: Pavel Fedin <p.fedin@samsung.com>
[k.kozlowski: Rebased on current v4.3]
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This new compatible string, "brcm,iproc-gpio", should be used for
all new iproc-based future SoCs.
Signed-off-by: Pramod Kumar <pramodku@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If GPIO controller's pins are muxed, pin-controller subsystem
need to be intimated by defining mapping between gpio and
pinmux controller. This patch adds required properties to
define this mapping via DT.
Signed-off-by: Pramod Kumar <pramodku@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add berlin4ct to existing berlin pinctrl device tree binding.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allwinner A83T soc port controller has 8 ports.
It has 3 IRQ banks namely PB, PG, PH.
Pinmuxing are different for some pins as compared to
sun8i A23 and A33.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
cycle
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing
all call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a
combined call to irq_set_chained_handler_and_data(). This
series was created by Thomas Gleixner after the problem was
observed by Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which
is way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs
from IRQ numbers. The goal is to get rid of the irq number
from the handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw
spinlocks in IRQ handlers to play nice with the realtime
patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner
sun4i driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC
subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.
Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage. Implement the pinconf
power-source parameter using these operations.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This part just add necessary change to boot imx6ul.
Update clock and pinctrl for imx6ul
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The current interrupt parsing code was working by accident, because the
default was actually parsing the first node of interrupts.
While that was mostly working (and the flags were actually ignored), this
binding has never been documented, and doesn't work with SoCs that have
multiple interrupt banks anyway.
Add a proper interrupt xlate function, that uses the same description than
the GPIOs (<bank> <pin> <flags>), that will make things less confusing.
The EINT number will still be used as the hwirq number, but won't be
exposed through the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl device tree binding documentation for the General Purpose Pin
Mapping module of the Conexant CX92755 SoC.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the pin controller probes before the GPIO driver it needs to
populate the GPIO driver state containers ahead of the actual
driver probe as the addresses are used by both halves of the
driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This introduces pinctrl drivers for gpio and mpp blocks found in family A
PMICs.
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "function" of the MPP driver was inherited from the GPIO driver, but the
differences between the two hardware blocks makes both the driver and the
device tree binding to be awkward.
Instead of overloading the "normal" function with various modes this patch
transposes the pinmux function to represent the three operating modes of the
MPP (digital, analog and current sink). The properties of pin pairing and DTEST
routing is moved to separate properties.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When the MPP is configured for analog output the output level is selected by
the AOUT_CTL register, this patch makes it possible to control this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "function", "pins" and "groups" pinmux and pinctrl properties have
been standardized. Support them in addition to the custom "renesas,*"
properties. New-style and old-style properties can't be mixed in DT.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MPP supports three modes; digital, analog and sink mode. This patch
implements support for the latter.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A whole lot of bug fixes. Nothing stands out here except the ability to
enable CONFIG_OF on every architecture, and an import of a newer version
of dtc.
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Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux
Pull devicetree updates from Grant Likely:
"A whole lot of bug fixes.
Nothing stands out here except the ability to enable CONFIG_OF on
every architecture, and an import of a newer version of dtc"
* tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux: (22 commits)
of/irq: Rename "intc_desc" to "of_intc_desc" to fix OF on sh
of/irq: Fix pSeries boot failure
Documentation: DT: Fix a typo in the filename "lantiq,<chip>-pinumx.txt"
of: define of_find_node_by_phandle for !CONFIG_OF
of/address: use atomic allocation in pci_register_io_range()
of: Add vendor prefix for Zodiac Inflight Innovations
dt/fdt: add empty versions of early_init_dt_*_memory_arch
of: clean-up unnecessary libfdt include paths
of: make unittest select OF_EARLY_FLATTREE instead of depend on it
of: make CONFIG_OF user selectable
MIPS: prepare for user enabling of CONFIG_OF
of/fdt: fix argument name and add comments of unflatten_dt_node()
of: return NUMA_NO_NODE from fallback of_node_to_nid()
tps6507x.txt: Remove executable permission
of/overlay: Grammar s/an negative/a negative/
of/fdt: Make fdt blob input parameters of unflatten functions const
of: add helper function to retrive match data
of: Grammar s/property exist/property exists/
of: Move OF flags to be visible even when !CONFIG_OF
scripts/dtc: Update to upstream version 9d3649bd3be245c9
...
As usual, quite a few device-tree updates in ARM land. There was ome
minor churn in DTs due to relicensing under a dual-license, and lots
of little additions of new peripherals, features etc, but nothing
really exciting to call to your attention. Some higlights, focsuing
on support for new SoCs and boards:
- AT91: new boards: Overkiz, Acme Systems' Arietta G25
- tegra: HDA support
- bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U
- mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
boards, DLink DNS-327L
- OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50
- ARM: added support for Juno r1 board
- sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G
- imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
Gateworks GW5510, and aristainetos2 boards
- hisilicon: hi6220 SoC support; new boards: 96boards hikey
Conflicts: None
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Kevin Hilman:
"As usual, quite a few device-tree updates in ARM land. There was one
minor churn in DTs due to relicensing under a dual-license, and lots
of little additions of new peripherals, features etc, but nothing
really exciting to call to your attention. Some higlights, focsuing
on support for new SoCs and boards:
- AT91: new boards: Overkiz, Acme Systems' Arietta G25
- tegra: HDA support
- bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS
RT-AC87U
- mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
boards, DLink DNS-327L
- OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill
SL50
- ARM: added support for Juno r1 board
- sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33,
Mele A1000G
- imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
Gateworks GW5510, and aristainetos2 boards
- hisilicon: hi6220 SoC support; new boards: 96boards hikey"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits)
ARM: hisi: revert changes from hisi/hip04-dt branch
ARM: nomadik: set proper compatible for accelerometer
ARM64: juno: add GPIO keys
ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes
ARM: dts: Introduce STM32F429 MCU
ARM: socfpga: dts: enable ethernet for Arria10 devkit
ARM: dts: k2l: fix the netcp range size
ARM: dts: k2e: fix the netcp range size
ARM: dts: k2hk: fix the netcp range size
ARM: dts: k2l-evm: Add device bindings for netcp driver
ARM: dts: k2e-evm: Add device bindings for netcp driver
ARM: dts: k2hk-evm: Add device bindings for netcp driver
ARM: BCM5301X: Add DT for Asus RT-AC87U
ARM: BCM5301X: add IRQ numbers for PCIe controller
ARM: BCM5301X: add NAND flash chip description
arm64: dts: Add dts files for Hisilicon Hi6220 SoC
clk: hi6220: Document devicetree bindings for hi6220 clock
arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
ARM: at91/dt: sama5d4ek: mci0 uses slot 0
ARM: at91/dt: kizbox: fix mismatch LED PWM device
...
To fix it, use the chance to rename according the compatible string,
which is "lantiq,pinctrl-falcon" and "lantiq,pinctrl-xway"
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: John Crispin <blogic@openwrt.org>
Signed-off-by: Rob Herring <robh@kernel.org>
The rk3368 is the first ARM64 soc from Rockchip, but seems to share most
peripherals with the ARM32 soc, including the pinctrl functionality.
The only notable difference is - as with every Rockchip soc - that the
offsets in the General Register Files moved around and a split of the pmu
section of the rk3288 into pmu and pmugrf (pmu general register files)
sections. The pinctrl driver of course only needs the pmugrf registers
for controlling the pin settings.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add PFC support for the R8A7794 SoC including pin groups for some
on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF...
Sergei: squashed together several patches, fixed the MLB_CLK typo,
added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin
group names, removed stray new line and fixed typos in the comments
in the pinmux_config_regs[] initializer, removed the platform device
ID, took into account limited number of signals in the GPIO1/5/6
controllers, added reasonable and removed unreasonable
copyrights, modified the bindings document, renamed, added changelog.
Changes in version 5:
- resolved rejects, refreshed the patch;
- added Laurent Pinchart's ACK.
Changes in version 4:
- reused the PORT_GP_26() macro to #define PORT_GP_28().
Changes in version 3:
- removed the platform device ID;
- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the
CPU_ALL_PORT() macro.
Changes in version 2:
- rebased the patch.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add device tree for i.MX7D SoC and imx7d-sdb board
- New i.MX6 board support: Armadeus Systems APF6, Gateworks GW5510,
and aristainetos2 boards
- Change LVDS to use simple-panel for nitrogen6x and sabrelite boards
- Add Wifi/Bluetooth devices support for cubox-i board
- Remove unused regulators and correct OTG roles setting for
imx6sl-warp board
- Add I2C support for imx23-olinuxino board
- Move imx6qdl HDMI device to a better place
- Add power-domain for imx6qdl CODA device
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Merge tag 'imx-dt-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
The i.MX device tree changes for 4.2:
- Add device tree for i.MX7D SoC and imx7d-sdb board
- New i.MX6 board support: Armadeus Systems APF6, Gateworks GW5510,
and aristainetos2 boards
- Change LVDS to use simple-panel for nitrogen6x and sabrelite boards
- Add Wifi/Bluetooth devices support for cubox-i board
- Remove unused regulators and correct OTG roles setting for
imx6sl-warp board
- Add I2C support for imx23-olinuxino board
- Move imx6qdl HDMI device to a better place
- Add power-domain for imx6qdl CODA device
* tag 'imx-dt-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
ARM: dts: imx6dl: add imx6dl gpt specific compatible string
ARM: dts: imx6: add DT for aristainetos2 board
ARM: dts: cubox-i/hummingboard: Fix the license text
ARM: dts: sabrelite: use simple-panel instead of display-timings for LVDS0
ARM: dts: nitrogen6x: use simple-panel instead of display-timings for LVDS0
ARM: dts: add imx7d-sdb support
ARM: dts: add imx7d soc dtsi file
ARM: dts: Armadeus Systems APF6 family support (i.MX6)
ARM: dts: vf610: Nomenclature fixup for PTC12 pin used in RMII mode.
ARM: dts: cubox-i: add support for Broadcom Wifi/Bluetooth devices
Document: dt: binding: imx: update document for imx7d support
ARM: dts: imx6qdl: Add power-domain phandle to CODA device node
ARM: dts: Gateworks GW5510 support (i.MX6)
ARM: dts: imx6sl-warp: Fix OTG roles
ARM: dts: imx6sl-warp: Remove USB regulators
ARM: dts: imx6sl-warp: Remove unused regulator
ARM: dts: add pinfunc include file to support imx7d
ARM: mxs: fix in tree users of ssd1306
ARM: dts: imx6qdl-hummingboard: Add PCIe support
ARM: dts: imx23-olinuxino: Add i2c support
...
The Armada 39x SoC family has grown a new variant, the Armada 395,
which sits between the Armada 390 and Armada 398 in terms of
features. This commit adds support for this additional variant to the
Armada 39x pinctrl driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 39x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 39x datasheet documents several new
PCIe related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 38x datasheet documents several new
PTP related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 38x datasheet documents several new
UART1 related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 38x datasheet documents several new
NAND related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada 38x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest Armada XP datasheet documents several new DRAM related
functions on various MPPs. This commit adds the description of these
new functions in the Armada XP pinctrl driver and its DT binding
documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada XP datasheet documents a new
NAND-related MPP function on MPP48, for which this commit adds
support.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest Armada XP datasheet documents that some of the MPP pins can
be used to access the second SPI bus, labelled 'spi1'. This commit
adds the corresponding pins in the pinctrl driver and its DT binding
documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.
In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.
This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the
'sck' subname and not 'clk', so this commit adjusts the code and
documentation accordingly.
Since this commit only changes the subname, DT backward compatibility
is not affected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For consistency with the datasheet, this commit renames the VDD
function of the MPP4 pin.
While this changes the DT compatibility, it is not considered to be a
problem since this pin is unlikely to be used for anything but
debugging purposes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There was an off-by-one in the documentation of the ge1(txd[0-3])
pins, which is fixed by this commit. Since the driver was correct, and
the subnames are anyway not used in the DT binding itself, there is no
need to push this documentation fix for stable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit normalizes the naming of the Ethernet txclkout pin to be
the same accross Marvell SoCs. It is worth mentioning that the DT
binding documentation of the Armada XP was wrong for MPP12: it said
the function was ge1(txd0), while it is in fact ge1(txclkout). It is
however not really a fix worth sending to stable since it does not
change the behavior, and the driver itself was correct.
Since only the subnames are changed, DT backward compatibility is not
affected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit aligns the naming of the audio 'lrclk' pin accross Marvell
SoCs.
Since only the subname is changed, the DT backward compatibility is
not affected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit normalizes the naming of PCIe pins to use 'rstout' instead
of 'rstoutn' or 'rst-out'.
Since only the subnames are changed, DT compatibility is not affected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit normalizes the naming of the TDM pins accross the
different Marvell SoCs. Mainly it consists in:
* Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn'
becomes 'rst'
* Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.
* Change the main name 'tdm-1' to 'tdm' for one of the pins of the
Armada XP
The last two changes affect DT compatibility, but since the TDM
interface is nowhere near being supported in mainline, it should not
be considered to be a serious problem at this point.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.
It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.
While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit modifies the definition of the Device Bus interface pins
to be consistent accross SoCs. Especially, it removes the 'n'
indicators that we don't encode in the subnames of pins:
'dev(wen0)' becomes 'dev(we0)'
'dev(wen1)' becomes 'dev(we1)'
'dev(oen)' becomes 'dev(oe)'
etc.
In addition, it fixes the Armada 375 DT binding documentation, which
forgot to document the 'dev' function for MPP46, MPP57 and MPP63.
Since only the subnames are changed, this commit does not affect DT
compatibility.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to be consistent with the datasheet and some other SoCs, this
commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".
While this changes the DT binding, this is not a problem since Armada
39x is a brand new SoC which isn't used in production yet (so now is
the right time to fix such things).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit makes the naming of SATA related MPP functions consistent
accross SoCs by adjusting the Armada 39x definition to use "prsnt"
instead of "present".
Since only the subnames are changed, the DT binding is not modified at
all.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit makes the dram functions naming (both the name and
subname) consistent accross SoC, by using:
dram(vttctrl)
dram(deccerr)
in all Marvell SoCs.
Due to the change to the name, it changes the DT binding, but these
functions are not used by any in-tree Device Tree file, and are very
unlikely to be used by anyone.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The subnames are purely informative, but it's nicer when they match
accross SoCs. This commit adjusts the Armada 375, Armada 38x and
Armada 39x MPP definitions so that the subnames of the PTP pins match
the ones used on Armada XP and Kirkwood.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There was a mistake in the definition of the functions for MPP48 on
Marvell Armada XP. The second function is dev(clkout), and not tclk.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After updating to a more recent version of the Armada XP datasheet, we
realized that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly
named "spi0-1" instead of just "spi0". This commit fixes that.
This DT binding change does not affect any of the in-tree users.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 5f597bb2be ("pinctrl: mvebu: add pinctrl driver for Armada 370")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A new revision of the Marvell Armada 38x hardware datasheet unveiled
that the definition of some of the PCIe functions were not
correct. This commit fixes the pinctrl driver accordingly.
Some PCIe functions simply do not exist, some of the PCIe functions in
fact were corresponding to other functions, and some PCIe functions
have been added.
Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related:
this function is in fact implemented on MPP43, instead of a PCIe
function.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ca6d9a084b ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This part just add necessary change to boot imx7d.
Update clock, pinctrl and gpt for imx7d
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The Pinctrl module (ioc) controls the Pad's function select
(each pad can have 8 functions), Pad's Drive Strength, Pad's
Pull Select and Pad's Input Disable status.
The ioc has two modules, ioc_top & ioc_rtc. Both of these two
modules have function select/clear, Pull select and Drive
Strength registers. But only ioc_rtc has input-disable
registers. The Pads on ioc_top have to access ioc_rtc to set
their input-disable status and intpu-disable-value.
So have to use one ioc driver instance to drive these two
ioc modules at the same time, and each ioc module will be
treat as one bank on the "IOC Device".
The GPIO Controller controls the GPIO status if the Pad has
been config as GPIO by Pinctrl already. Includes the GPIO
Input/output, Interrupt type, Interrupt Status, and Set/Get
Values.
The GPIO pull up/down are controlled by Pinctrl.
There are 7 GPIO Groups and splited into 3 MACROs in atlas7.
The GPIO Groups in one MACRO share one GPIO controllers, each
GPIO Group are treated as one GPIO bank.
For example:
In VDIFM macro, there is one GPIO Controller, it has 3 banks
to control 3 gpio groups. Its gpio name space is from 0 to 95.
The Device Tree can be written as following:
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>;
gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp";
bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp".
bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp".
bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp".
Signed-off-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since 6397 is no need to support interrupt controller,
moving interrupt controller relate property to optional list.
Also adding mt8173 and mt8127 to bindings.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Berlin pinctrl documentation was part of the Marvell Berlin SoC
documentation because the Berlin pinctrl configuration was inside the
chip and the system controllers. With the recent rework of the chip and
system controller handling (now an MFD driver registers all sub-devices
of the two soc and system controller nodes and each device has its own
sub-node), the documentation of the Berlin pinctrl driver can be moved
to the generic pinctrl documentation directory.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.
This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:
pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};
mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}
conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};
conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};
conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};
conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently the "function" + "groups" combination is the only documented
format for pinmux nodes, although many drivers use "function" + "pins".
Update the generic pinctrl binding to include the "function" + "pins"
combination as well.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinconf_generic_dt_node_to_map() scans only subnodes of the pinctrl-0 pahndle,
not the referenced node itself. Change the example nodes to match.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra210's pinmux supports a different set of pins/options than earlier
SoCs, so requires its own driver (well, table of pin-specific data).
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- DT unittests for I2C probing and overlays from Pantelis Antoniou
- Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha
- Add Tegra compatible strings missing for newer parts from Paul
Walmsley
- Various vendor prefix additions
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Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull DeviceTree changes from Rob Herring:
- DT unittests for I2C probing and overlays from Pantelis Antoniou
- Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha
- Add Tegra compatible strings missing for newer parts from Paul
Walmsley
- Various vendor prefix additions
* tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
of: Add vendor prefix for OmniVision Technologies
of: Use ovti for Omnivision
of: Add vendor prefix for Truly Semiconductors Limited
of: Add vendor prefix for Himax Technologies Inc.
of/fdt: fix sparse warning
of: unitest: Add I2C overlay unit tests.
Documentation: DT: document compatible string existence requirement
Documentation: DT bindings: add nvidia, tegra132-denver compatible string
Documentation: DT bindings: add more Tegra chip compatible strings
of: EXPORT_SYMBOL_GPL of_property_read_u64_array
of: Fix brace position for struct of_device_id definition
of/unittest: Remove obsolete code
dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt
Add AD Holdings Plc. to vendor-prefixes.
dt-bindings: Add Silicon Mitus vendor prefix
Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol
pinctrl: fix up device tree bindings
DT: Vendors: Add Everspin
doc: add bindings document for altera fpga manager
drivers: of: Export of_reserved_mem_device_{init,release}
Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:
http://marc.info/?l=devicetree&m=142255654213019&w=2
The primary objective here is to avoid checkpatch warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
DT binding text files have been updated for the following IP blocks:
- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY
N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.
This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:
- Per-IP block patches have been combined into a single patch
- Explicit documentation about which compatible strings are actually
matched by the driver has been removed. In its place is implicit
documentation that loosely follows Rob's prescribed format:
"Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
<chip> is tegra30, tegra132, ..." [...] "You should attempt to
document known values of <chip> if you use it"
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Remove the DT compatible string entry for the now unsupported sh7372 SoC.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add PFC support for the EMMA Mobile EV2 SoC including pin groups for
on-chip devices.
Signed-off-by: Niklas Söderlund <niso@kth.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Audio IPs on Exynos7 require gpios available in AUDIO
pin controller block. So adding the AUDIO pinctrl support.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.
The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After the Nomadik pin controller was force migrated to generic pin
control bindings, some leftovers in the documentation need to be
cleaned up. The code and device trees are already migrated.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Add documentation for the devicetree binding for the Zynq pincontroller.
Changes since v1:
- fix typo
- add USB related documentation
- remove 'pinctrl-' prefix for pinctrl sub-nodes
- update documentation to enforce strict separation of pinmux
and pinconf nodes
- update example accordingly
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After the Nomadik pin controller was force migrated to generic pin
control bindings, some leftovers in the documentation need to be
cleaned up. The code and device trees are already migrated.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Force conversion of the ux500 pin control device trees
and parsers to use the generic pin control bindings.
- New driver and device tree bindings for the Qualcomm
PMIC MPP pin controller and GPIO.
- Some ACPI infrastructure for pin controllers.
- New driver for the Intel CherryView/Braswell pin controller,
the first Intel pin controller to fully take advantage of
the pin control subsystem.
- Support the Freescale i.MX VF610 variant.
- Support the sunxi A80 variant.
- Support the Samsung Exynos 4415 and Exynos 7 variants.
- Split out Intel pin controllers to their own subdirectory.
- A large slew of rockchip pin control updates, including
suspend/resume support.
- A large slew of Samsung Exynos pin controller updates.
- Various minor updates and fixes.
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Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"Here is a stash of pin control changes I have collected for the v3.19
series. Mainly new hardware support, with Intels new embedded SoC as
the especially interesting thing standing out, fully using the
subsystem.
- Force conversion of the ux500 pin control device trees and parsers
to use the generic pin control bindings.
- New driver and device tree bindings for the Qualcomm PMIC MPP pin
controller and GPIO.
- Some ACPI infrastructure for pin controllers.
- New driver for the Intel CherryView/Braswell pin controller, the
first Intel pin controller to fully take advantage of the pin
control subsystem.
- Support the Freescale i.MX VF610 variant.
- Support the sunxi A80 variant.
- Support the Samsung Exynos 4415 and Exynos 7 variants.
- Split out Intel pin controllers to their own subdirectory.
- A large slew of rockchip pin control updates, including
suspend/resume support.
- A large slew of Samsung Exynos pin controller updates.
- Various minor updates and fixes"
* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
pinctrl: meson: add device tree bindings documentation
gpio: tz1090: Fix error handling of irq_of_parse_and_map
pinctrl: tz1090-pinctrl.txt: Fix typo in binding
pinctrl: pinconf-generic: Declare dt_params/conf_items const
pinctrl: exynos: Add support for Exynos4415
pinctrl: exynos: Add initial driver data for Exynos7
pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
pinctrl: exynos: Consolidate irq domain callbacks
pinctrl: exynos: Generalize the eint16_31 demux code
pinctrl: samsung: Separate per-bank init and runtime data
pinctrl: samsung: Constify samsung_pin_ctrl struct
pinctrl: samsung: Constify samsung_pin_bank_type struct
pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
pinctrl: Add Intel Cherryview/Braswell pin controller support
gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
pinctrl: Fix path error in documentation
pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
pinctrl: rockchip: add suspend/resume functions
...
A misspelled 'arbitrary' propagated to quite a few locations in the DT
binding documentation for pin-controllers. Fixing by:
git grep abitrary | cut -f1 -d: | xargs sed -i 's/abitrary/arbitrary/'
Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
This introduced the device tree bindings for the GPIO block found
in PMIC's from Qualcomm.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After force converting the ABx500 bindings in the driver and
device tree sources, also update the binding documentation to
state that we are now using standard bindings.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
development series:
- New drivers for the Freescale i.MX21, Qualcomm APQ8084
pin controllers.
- Incremental new features on the Rockchip, atlas 6,
OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin
and Nomadik.
- Push Freescale drivers down into their own subdirectory.
- Assorted sprays of syntax and semantic fixes.
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Merge tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"This is the bulk of pin control changes for the v3.18 development
series:
- New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin
controllers.
- Incremental new features on the Rockchip, atlas 6, OMAP, AM437x,
APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik.
- Push Freescale drivers down into their own subdirectory.
- Assorted sprays of syntax and semantic fixes"
* tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: specify bindings for pins and groups
pinctrl: nomadik: improve GPIO debug prints
pinctrl: abx500: refactor DT parser to take two paths
pinctrl: abx500: use helpers for map allocation/free
pinctrl: alter device tree bindings for functions
pinctrl: nomadik: refactor DT parser to take two paths
pinctrl: nomadik: use utils map free function
pinctrl: nomadik: use util function to reserve maps
pinctrl: qcom: use restart_notifier mechanism for ps_hold
pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation
pinctrl: berlin: fix the dt_free_map function
pinctrl: at91: disable PD or PU before enabling PU or PD
pinctrl: st: remove gpiochip in failure cases
pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add
pinctrl: at91: Fix failure path in at91_gpio_probe path
pinctrl: lantiq: Release gpiochip resources in fail case
pinctrl: imx: detect uninitialized pins
pinctrl: tegra: Add MIPI pad control
pinctrl: at91: Switch to using managed clk_get
pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges
...
Pin configurations can be per-pin or per-group. Make sure that the
per-group case is covered by the bindings.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For function and group configuration nodes, use "function"
"groups" string pairs, not "pins" where there should be
"groups".
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.
Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.
The register is not yet documented in the TRM, here is
the description:
70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
[31:02] RESERVED
[01:01] DSIB_MODE [CSI=0,DSIB=1]
[00:00] RESERVED
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The drive strength patched introduced the atmel,sama5d-pinctrl
compatible string. Drive strength is now an option for the
CONFIG bits per pin. Also added note about MULTIDRIVE being
equivalent to open-drain output and added missing "s" at the
end of need everywhere in the bits descriptions.
Signed-off-by: Marek Roszko <mark.roszko@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin
controller inside the APQ8084.
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a function ps_hold (Power Suppy Hold Signal) in pinctrl-ap8064
documentation which was missing. This function is used to reset the targets
with apq8064 soc.
CC: "Ivan T. Ivanov" <iivanov@mm-sol.com>
CC: Stephen Boyd <sboyd@codeaurora.org>
CC: Andy Gross <agross@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[nm@ti.com: minor updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add basic skeleton of OMAP pinctrl bindings. This is compatible with
pinctrl,single bindings and is meant purely as a reference point.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The example in the binding document indicates that interrupt 32 is used
for the TLMM summary IRQ. Correct this to reduce the confusion.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new platforms,
but there's also a bit of cleanup and code removal for things that
are moved from platform code to DT contents (some OMAP clock code in
particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no particular
order:
* Rockchip RK3288 SoC support, including DTS for a dev board that they
have seeded with some community developers.
* Better support for Hardkernel Exynos4-based ODROID boards.
* CCF conversions (and dtsi contents) for several Renesas platforms.
* Gumstix Pepper (TI AM335x) board support
* TI eval board support for AM437x
* Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an Ippo
tablet with the chipset.
* Allwinner A31 Hummingbird board support, not to be confused with the
SolidRun i.MX-based Hummingboard.
* Tegra30 Apalis board support
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Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
Instead of relying on pinmux->disable(), make the gpio function an
explicit function for all pins that supports it.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the device tree binding documentation for the XUSB pad
controller found on NVIDIA Tegra SoCs. It exposes both pinmuxing and PHY
capabilities.
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The driver already supports the r8a7791 SoC, and "renesas,pfc-r8a7791"
is already in use.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins, which is useful for pins that are not supposed to be used by
any dedicated driver, but need certain board-specific setting.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but with different parameters very inconvenient.
This patch implements Tegra-like support for grouping multiple pinctrl
groups inside one device tree node, by completely changing the way
pin groups and functions are parsed from device tree. The code creating
pinctrl maps from DT nodes has been borrowed from pinctrl-tegra, while
the initial creation of groups and functions has been completely
rewritten with following assumptions:
- each group consists of just one pin and does not depend on data
from device tree,
- each function is represented by a device tree child node of the
pin controller, which in turn can contain multiple child nodes
for pins that need to have different configuration values.
Device Tree bindings are fully backwards compatible. New functionality
can be used by defining a new pinctrl group consisting of several child
nodes, as on following example:
sd4_bus8: sd4-bus-width8 {
part-1 {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
part-2 {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <4>;
samsung,pin-pud = <4>;
samsung,pin-drv = <3>;
};
};
Tested on Exynos4210-Trats board and a custom Exynos4212-based one.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC.
Add support for the pins controlled by the R_PIO controller.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin-controller of the new RK3288 contains all the quirks just added in
the previous patches.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Upcoming Rockchip SoCs have additional quirks to handle. Currently they would
be handled by giving the bank a special compatible property. But the nature
of the new quirks would require a lot of them. Also as we want to move to the
separate dw_gpio driver in the future, these bank-definitions should be
extended at all.
Describing the bank quirks this way also enables us to deprecate the special
bank compatible string for bank0 on rk3188 and simplify the handling code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull trivial tree changes from Jiri Kosina:
"Usual pile of patches from trivial tree that make the world go round"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (23 commits)
staging: go7007: remove reference to CONFIG_KMOD
aic7xxx: Remove obsolete preprocessor define
of: dma: doc fixes
doc: fix incorrect formula to calculate CommitLimit value
doc: Note need of bc in the kernel build from 3.10 onwards
mm: Fix printk typo in dmapool.c
modpost: Fix comment typo "Modules.symvers"
Kconfig.debug: Grammar s/addition/additional/
wimax: Spelling s/than/that/, wording s/destinatary/recipient/
aic7xxx: Spelling s/termnation/termination/
arm64: mm: Remove superfluous "the" in comment
of: Spelling s/anonymouns/anonymous/
dma: imx-sdma: Spelling s/determnine/determine/
ath10k: Improve grammar in comments
ath6kl: Spelling s/determnine/determine/
of: Improve grammar for of_alias_get_id() documentation
drm/exynos: Spelling s/contro/control/
radio-bcm2048.c: fix wrong overflow check
doc: printk-formats: do not mention casts for u64/s64
doc: spelling error changes
...
development cycle:
- Antoine Tenart made the get_group_pins() vtable entry
optional.
- Antoine also provides an entirely new driver for the
Marvell Berlin SoC. This is unrelated to the existing
MVEBU hardware driver and warrants its own separate
driver.
- Reflected from the GPIO subsystem there is a number of
refactorings to make pin control drivers with gpiochips
use the new gpiolib irqchip helpers. The following
drivers were converted to use the new infrastructure:
- ST Microelectronics STiH416 and friends
- The Atmel AT91
- The CSR SiRF (Prima2)
- The Qualcomm MSM series
- Massive improvements in the Qualcomm MSM driver from
Bjorn Andersson, Andy Gross and Kumar Gala. Among those
new support for the IPQ8064 and MSM8x74 SoC variants.
- Support for the Freescale i.MX6 SoloX SoC variant.
- Massive improvements in the Allwinner sunxi driver from
Boris Brezillon, Maxime Ripard and Chen-Yu Tsai.
- Renesas PFC updates from Laurent Pinchart, Kuninori
Morimoto, Wolfram Sang and Magnus Damm.
- Cleanups and refactorings of the nVidia Tegra driver from
Stepgen Warren.
- The Exynos driver now supports the Exynos3250 SoC.
- Intel BayTrail updates from Jin Yao, Mika Westerberg.
- The MVEBU driver now supports the Orion5x SoC
variants, which is part of the effort of getting rid of
the old Marvell kludges in arch/arm/mach-orion5x
- Rockchip driver updates from Heiko Stuebner.
- A ton of cleanups and janitorial patches from Axel Lin.
- Some minor fixes and improvements here and there.
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Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next
Pull pin control changes from Linus Walleij:
"This is the bulk of pin control changes for the v3.16 development
cycle:
- Antoine Tenart made the get_group_pins() vtable entry optional.
- Antoine also provides an entirely new driver for the Marvell Berlin
SoC. This is unrelated to the existing MVEBU hardware driver and
warrants its own separate driver.
- reflected from the GPIO subsystem there is a number of refactorings
to make pin control drivers with gpiochips use the new gpiolib
irqchip helpers. The following drivers were converted to use the
new infrastructure:
* ST Microelectronics STiH416 and friends
* The Atmel AT91
* The CSR SiRF (Prima2)
* The Qualcomm MSM series
- massive improvements in the Qualcomm MSM driver from Bjorn
Andersson, Andy Gross and Kumar Gala. Among those new support for
the IPQ8064 and MSM8x74 SoC variants.
- support for the Freescale i.MX6 SoloX SoC variant.
- massive improvements in the Allwinner sunxi driver from Boris
Brezillon, Maxime Ripard and Chen-Yu Tsai.
- Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto,
Wolfram Sang and Magnus Damm.
- Cleanups and refactorings of the nVidia Tegra driver from Stepgen
Warren.
- the Exynos driver now supports the Exynos3250 SoC.
- Intel BayTrail updates from Jin Yao, Mika Westerberg.
- the MVEBU driver now supports the Orion5x SoC variants, which is
part of the effort of getting rid of the old Marvell kludges in
arch/arm/mach-orion5x
- Rockchip driver updates from Heiko Stuebner.
- a ton of cleanups and janitorial patches from Axel Lin.
- some minor fixes and improvements here and there"
* tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
pinctrl: sirf: fix a bad conflict resolution
pinctrl: msm: Add more MSM8X74 pin definitions
pinctrl: qcom: ipq8064: Fix naming convention
pinctrl: msm: Add missing sdc1 and sdc3 groups
pinctrl: sirf: switch to using allocated state container
pinctrl: Enable "power-source" to be extracted from DT files
pinctrl: sunxi: create irq/pin mapping during init
pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
pinctrl: berlin: Use devm_ioremap_resource()
pinctrl: sirf: fix typo for GPIO bank number
pinctrl: sunxi: depend on RESET_CONTROLLER
pinctrl: sunxi: fix pin numbers passed to register offset helpers
pinctrl: add pinctrl driver for imx6sx
pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
pinctrl: msm: switch to using generic GPIO irqchip helpers
pinctrl: sunxi: Fix multiple registration issue
pinctrl: sunxi: Fix recursive dependency
pinctrl: berlin: add the BG2CD pinctrl driver
pinctrl: berlin: add the BG2 pinctrl driver
pinctrl: berlin: add the BG2Q pinctrl driver
...
Add "power-source" property to generic options used for DT parsing files.
This enables drivers, which use generic pin configurations, to get the
value passed to this property.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Introduce the syscons for grf and pmu and deprecate the previous register
areas.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.
The now deprecated register is still supported though.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
s/interrupts-names/interrupt-names/g
s/clocks-names/clock-names/g
Some of the binding files and device tree files get this wrong and the
kernel won't be able to pick it up. Fix them up now so that they don't
get widely used.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by : Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
functionality this time, just incremental driver updates:
- A large refactoring of the MVEBU (Marvell) driver.
- A large refactoring of the Tegra (nVidia) driver.
- GPIO interrupt including soft edges support in the
STi driver.
- Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung),
sunxi (AllWinner), i.MX (Freescale), Baytrail.
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Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk changes from Linus Walleij:
"Pin control bulk changes for the v3.15 series, no new core
functionality this time, just incremental driver updates:
- A large refactoring of the MVEBU (Marvell) driver.
- A large refactoring of the Tegra (nVidia) driver.
- GPIO interrupt including soft edges support in the STi driver.
- Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
(AllWinner), i.MX (Freescale), Baytrail"
* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: tegra: add some missing Tegra114 entries
pinctrl: tegra: fix some mistakes in Tegra124
pinctrl: msm: fix up out-of-order merge conflict
pinctrl: st: Fix error check for of_irq_to_resource usage
pinctrl: tegra: consistency cleanup
pinctrl: tegra: dynamically calculate function list of groups
pinctrl: tegra: init Tegra20/30 at module_init time
pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
pinctrl: st: add pinctrl support for the STiH407 SoC
pinctrl: st: Enhance the controller to manage unavailable registers
pinctrl: msm: Simplify msm_config_reg() and callers
pinctrl: msm: Remove impossible WARN_ON()s
pinctrl: msm: Replace lookup tables with math
pinctrl: msm: Drop OF_IRQ dependency
pinctrl: msm: Drop unused includes
pinctrl: msm: Check for ngpios > MAX_NR_GPIO
pinctrl: msm: Silence recursive lockdep warning
pinctrl: mvebu: silence WARN to dev_warn
pinctrl: msm: drop wake_irqs bitmap
pinctrl-baytrail: add function mux checking in gpio pin request
...
The compatible string doesn't have an x in it. Fix it. Also
remove the "qcom" prefix from pins and functions as this binding
uses the generic pinctrl bindings for the pins and functions.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dove pinctrl binding now requires three different reg properties. This
updates corresponding binding and example accordingly. While at it, also
document reg property as required for the other MVEBU SoC pinctrl nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The compatible string of the Broadcom Capri pinctrl driver is renamed to
"brcm,bcm11351-pinctrl" to match the machine binding here:
Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Adds pinctrl support for all platforms based on EXYNOS5260 SoC.
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch add interrupt support to the pincontroller driver.
ST Pincontroller GPIO bank can have one of the two possible types of
interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of overall interrupts numbers required. All
these banks belong to a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove extra comma in pinctrl-single documentation.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds slew-rate and input-enable/disable support for pinconf
-generic.
Signed-off-by: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the more specific form 8974 for the compatible to reduce the
risk of future mishaps.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This device tree binding document describes the Tegra124 pincontrol
DT bindings. This document lists all valid properties, names, mux
options of Tegra124 pins.
Changes from V1:
- Referred the dt-binding header file on describing the nodes.
Changes from V2:
- Rewording reg properties.
- drop drv_type as it is not applicable.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On non-DT platforms IRQ controllers associated with the GPIOs have a
fixed IRQ base value known at compile time. The sh-pfc driver translates
GPIO number to IRQ numbers using a hardcoded table. This mechanism
breaks on DT platforms, as the IRQ base values are dynamic in that case.
Fix this by specifying IRQs associated with GPIOs in IRQ resources,
populated automatically from the device tree. When IRQ resources are
specified the driver requires one IRQ resource per GPIO able to generate
an interrupt, and uses the translation table to compute the IRQ resource
offset instead of the IRQ number.
Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This is mostly cut and paste from the imx35 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx25.h.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Support gpio devicetree subnodes to allow a more detailed DT hardware
description.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Blackfin ADI pin control driver, we move yet another
architecture under this subsystem umbrella.
- Incremental updates to the Renesas Super-H PFC pin control
driver. New subdriver for the r8a7791 SoC.
- Non-linear GPIO ranges from the gpiolib side of things,
this enabled simplified device tree bindings by referring
entire groups of pins on some pin controller to act as
back-end for a certain GPIO-chip driver.
- Add the Abilis TB10x pin control driver used on the ARC
architecture. Also the corresponding GPIO driver is merged
through this tree, so the ARC has full support for pins
and GPIOs after this.
- Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin
controller instances. The i.MX1 and i.MX27 is an entirely
new family (silicon) of controllers whereas i.MX50 is
a variant of the previous supported controller.
- Then the usual slew of fixes, cleanups and incremental
updates.
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Merge tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Main pin control pull request for the v3.13 cycle.
The changes hitting arch/blackfin are ACKed by the Blackfin
maintainer, and the device tree bindings are ACKed to the extent
possible by someone from the device tree maintainers group.
- Blackfin ADI pin control driver, we move yet another architecture
under this subsystem umbrella.
- Incremental updates to the Renesas Super-H PFC pin control driver.
New subdriver for the r8a7791 SoC.
- Non-linear GPIO ranges from the gpiolib side of things, this
enabled simplified device tree bindings by referring entire groups
of pins on some pin controller to act as back-end for a certain
GPIO-chip driver.
- Add the Abilis TB10x pin control driver used on the ARC
architecture. Also the corresponding GPIO driver is merged through
this tree, so the ARC has full support for pins and GPIOs after
this.
- Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller
instances. The i.MX1 and i.MX27 is an entirely new family
(silicon) of controllers whereas i.MX50 is a variant of the
previous supported controller.
- Then the usual slew of fixes, cleanups and incremental updates"
The ARC DT changes are apparently still pending, that hopefully gets
sorted out in a timely manner.
* tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: imx50: add pinctrl support code for the IMX50 SoC
pinctrl: at91: copy define to driver
pinctrl: remove minor dead code
pinctrl: imx: fix using pin->input_val wrongly
pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe()
gpio: tb10x: fix return value check in tb10x_gpio_probe()
gpio: tb10x: use module_platform_driver to simplify the code
pinctrl: imx27: imx27 pincontrol driver
pinctrl: imx1 core driver
pinctrl: sh-pfc: r8a7791 PFC support
sh-pfc: r8a7778: Add CAN pin groups
gpio: add TB10x GPIO driver
pinctrl: at91: correct a few typos
pinctrl: mvebu: remove redundant of_match_ptr
pinctrl: tb10x: use module_platform_driver to simplify the code
pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe()
pinctrl: add documentation for pinctrl_get_group_pins()
pinctrl: rockchip: emulate both edge triggered interrupts
pinctrl: rockchip: add rk3188 specifics
pinctrl: rockchip: remove redundant check
...
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Use macros for mxs pinctrl settings
* New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3
* Support DSPI device for vf610
* Add PCIe device for imx6qdl
* Add UHS pinctrl states for imx6sl and imx6qdl
* Display support for APF and imx51-babbage boards
* Enable SPI NOR and USB for imx6sl-evk board
* Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard
* Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc.
* Some random updates on imx51 device tree
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Merge tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
The imx/mxs device tree changes for 3.13:
- Use macros for mxs pinctrl settings
- New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3
- Support DSPI device for vf610
- Add PCIe device for imx6qdl
- Add UHS pinctrl states for imx6sl and imx6qdl
- Display support for APF and imx51-babbage boards
- Enable SPI NOR and USB for imx6sl-evk board
- Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard
- Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc.
- Some random updates on imx51 device tree
* tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (44 commits)
ARM: imx: imx6sl iomuxc syscon is compatible to imx6q
ARM: dts: imx6sl-evk: enable the SPI NOR
ARM: dts: imx6sl: add a pinctrl for ECSPI1
ARM: imx27: add missing #pwm-cells property
ARM: dts: imx6sl: add pinctrl uhs states for usdhc
ARM: dts: imx6qdl-sabresd: Add backlight support for lvds
ARM: dts: imx51-babbage: Make DVI and WVGA panel functional
ARM: imx27-apf27dev: Add framebuffer support
ARM: imx51-apf51dev: Add parallel display support
ARM: dts: imx53-qsb: Do not use GPIO1_8 as wakeup source
ARM: dts: imx53-qsb: SDHC1 does not have cd-gpios
ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode
ARM: dts: mxs: Add MSR M28CU3 board
ARM: dts: imx6qdl-wandboard: Provide phy-reset-gpios
ARM: dts: imx6qdl-sabresd: Provide phy-reset-gpios
ARM: dts: imx6q-sabrelite: Add ethernet phy reset pin into hog
ARM: dts: imx6qdl: add pcie device node
ARM: dts: imx6q-udoo: Add initial board support
ARM: dts: mxs: Add muxing options for the SSP2 MMC
ARM: dts: add initial VF610 Cosmic/Cosmic+ board support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Besides the pull registers sitting in a separate place, the rk3188 also
has the peculiarity that the pull registers of the first bank are split
and the first half is sitting in the register space of the pmu.
Therefore this adds a special bank-type for the first bank, to handle
the two register sources.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin control registers can have interrupts for example
for device wake-up. These interrupts can be treated as a
chained interrupt controller as suggested earlier by
Linus Walleij <linus.walleij@linaro.org>.
This patch adds support for interrupts in a way that
should be pretty generic, and works for the omaps that
support wake-up interrupts. On omaps, there's an
interrupt enable and interrupt status bit for each pin.
The two pinctrl domains on omaps share a single interrupt
from the PRM chained interrupt handler. Support for
other similar hardware should be easy to add.
Note that this patch does not attempt to handle the
wake-up interrupts automatically unlike the earlier
patches. This patch allows the device drivers to do
a request_irq() on the wake-up pins as needed. I'll
try to do also a separate generic patch for handling
the wake-up events automatically.
Also note that as this patch makes the pinctrl-single
an irq controller, the current bindings need some
extra trickery to use interrupts from two different
interrupt controllers for the same driver. So it
might be worth waiting a little on the patches
enabling the wake-up interrupts from drivers as there
should be a generic way to handle it coming. And also
there's been discussion of interrupts-extended binding
for using interrupts from multiple interrupt controllers.
In any case, this patch should be ready to go allowing
handling the wake-up interrupts in a generic way, or
separately from the device drivers.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: Roger Quadros <rogerq@ti.com>
Cc: linux-kernel@vger.kernel.org
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: devicetree@vger.kernel.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
While commit e164153 (pinctrl: imx: move hard-coding data into device
tree) moves to use DTC macro for imx pinctrl device tree setting, it
changes the semantics of fsl,pins without updating the bindings doc
properly. Let's update the fsl,pins description to stop confusing
people.
While at it, the example in the document is updated, and the stale TODO
gets removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Palmas devices do not support the default bias configuration
and hence removing this option from valid pin config parameters.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add missing "atmel,at91sam9x5-pinctrl" compatible string to the
documentation.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove the list of possible pin configurations from the documentation
file and create header files containing those definitions.
This eliminates the need for error-prone manual lookup of those values
in the documentation and guarantees consistency between the human
readable representation of the pad function in the .dts file and the
actual binary value used in DT.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Device tree and bindings updates for 3.12.
General additions of various on-chip and on-board peripherals on various
platforms as support gets added. Some of the bigger changes are:
- Addition of (new) PCI-e support on Tegra.
- More Tegra4 support, including PMC configuration for Dalmore.
- Addition of a new board for Exynos4 (trats2) and more bindings for 4x12 IP.
- Addition of Allwinner A20 and A31 SoC and board files.
- Move of the ST Ericsson device tree files to now use ste-* prefix.
- More move of hardware description of shmobile platforms to DT.
- Two new board dts files for Freescale MXs.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"Device tree and bindings updates for 3.12.
General additions of various on-chip and on-board peripherals on
various platforms as support gets added. Some of the bigger changes
are:
- Addition of (new) PCI-e support on Tegra.
- More Tegra4 support, including PMC configuration for Dalmore.
- Addition of a new board for Exynos4 (trats2) and more bindings for
4x12 IP.
- Addition of Allwinner A20 and A31 SoC and board files.
- Move of the ST Ericsson device tree files to now use ste-* prefix.
- More move of hardware description of shmobile platforms to DT.
- Two new board dts files for Freescale MXs"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (177 commits)
dts: Rename DW APB timer compatible strings
dts: Deprecate ALTR as a vendor prefix
of: add vendor prefix for Altera Corp.
ARM: at91/dt: sam9x5ek: add sound configuration
ARM: at91/dt: sam9x5ek: enable SSC
ARM: at91/dt: sam9x5ek: add WM8731 codec
ARM: at91/dt: sam9x5: add SSC DMA parameters
ARM: at91/dt: add at91rm9200 PQFP package version
ARM: at91: at91rm9200: set default mmc0 pinctrl-names
ARM: at91: at91sam9n12: correct pin number of gpio-key
ARM: at91: at91sam9n12: add qt1070 support
ARM: at91: at91sam9n12: add pinctrl of TWI
ARM: at91: Add PMU support for sama5d3
ARM: at91: at91sam9260: add missing pinctrl-names on mmc
ARM: tegra: configure power off for Dalmore
ARM: DT: binding fixup to align with vendor-prefixes.txt (DT)
ARM: dts: add sdio blocks to bcm28155-ap board
ARM: dts: align sdio numbers to HW definition
ARM: sun7i: Add Olimex A20-Olinuxino-Micro support
ARM: sun7i: Add Allwinner A20 DTSI
...
Pull trivial tree from Jiri Kosina:
"The usual trivial updates all over the tree -- mostly typo fixes and
documentation updates"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (52 commits)
doc: Documentation/cputopology.txt fix typo
treewide: Convert retrun typos to return
Fix comment typo for init_cma_reserved_pageblock
Documentation/trace: Correcting and extending tracepoint documentation
mm/hotplug: fix a typo in Documentation/memory-hotplug.txt
power: Documentation: Update s2ram link
doc: fix a typo in Documentation/00-INDEX
Documentation/printk-formats.txt: No casts needed for u64/s64
doc: Fix typo "is is" in Documentations
treewide: Fix printks with 0x%#
zram: doc fixes
Documentation/kmemcheck: update kmemcheck documentation
doc: documentation/hwspinlock.txt fix typo
PM / Hibernate: add section for resume options
doc: filesystems : Fix typo in Documentations/filesystems
scsi/megaraid fixed several typos in comments
ppc: init_32: Fix error typo "CONFIG_START_KERNEL"
treewide: Add __GFP_NOWARN to k.alloc calls with v.alloc fallbacks
page_isolation: Fix a comment typo in test_pages_isolated()
doc: fix a typo about irq affinity
...
This patch implements pinctrl support and adds device tree bindings
for s5pv210.
Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This branch contains all *.dts (device tree) changes for Tegra.
New features enabled are:
* PMICs on Dalmore
* CPU power-gating on Dalmore
* HDMI output on Beaver
* LP1 system suspend mode on almost all boards
* PCIe support on numerous Tegra20/30 boards
* USB support on Tegra30/114 boards
* Audio capture on Beaver and Dalmore
* Temperature sensor on Cardhu.
... along with a few DT cleanups.
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Merge tag 'tegra-for-3.12-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From: Stephen Warren:
ARM: tegra: device tree changes for 3.12
This branch contains all *.dts (device tree) changes for Tegra.
New features enabled are:
* PMICs on Dalmore
* CPU power-gating on Dalmore
* HDMI output on Beaver
* LP1 system suspend mode on almost all boards
* PCIe support on numerous Tegra20/30 boards
* USB support on Tegra30/114 boards
* Audio capture on Beaver and Dalmore
* Temperature sensor on Cardhu.
... along with a few DT cleanups.
* tag 'tegra-for-3.12-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits)
ARM: tegra: add Mic Jack to Dalmore device tree
ARM: tegra: add Mic Jack to Beaver device tree
ARM: tegra: add USB DT entries for Tegra114, Dalmore
ARM: tegra: add USB DT entries for Tegra30
ARM: dts: tegra: Increase prefetchable PCI memory space
ARM: tegra: Fix Beaver's PCIe lane configuration
ARM: tegra: Enable PCIe controller on Beaver
ARM: tegra: Enable PCIe controller on Cardhu
ARM: tegra: Add Tegra30 PCIe support
ARM: tegra: trimslice: Initialize PCIe from DT
ARM: tegra: harmony: Initialize PCIe from DT
ARM: tegra: tec: Add PCIe support
ARM: tegra: tamonten: Add PCIe support
ARM: tegra: Add Tegra20 PCIe support to DT
ARM: tegra: enable LP1 suspend mode
ARM: tegra: beaver: Enable HDMI output
ARM: tegra: use TEGRA_GPIO() in a couple more places
ARM: tegra: dalmore: fix the irq trigger type of Palmas MFD device
ARM: tegra: define valid function names in DT document
ARM: tegra: dalmore: add PM configurations for PMC
...
TI Palmas series Power Management IC have multiple pins which can be
configured for different functionality. This pins can be configured
for different function. Also their properties like pull up/down,
open drain enable/disable are configurable.
Add support for pincontrol driver Palmas series device like TPS65913,
TPS80036. The driver supports to be register from DT only.
Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Add ack by Lee.
- Correct the binding docs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl bindings can benefit from generic property names that define
which pins a "pin configuration node" affects, and which mux function
to select onto those pins. Document new properties for this purpose so
that other bindings may refer to them.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reword the section of pinctrl-bindings.txt that describes generic
properties that pinctrl bindings may use. The aim is to make the text
clearer, and more explicitly call out the responsibility of individual
bindings that use the generic properties to define which of the
properties are used, and how.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change compatible string to something more standard.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- A large slew of improvements of the Genric pin configuration
support, and deployment in four different platforms:
Rockchip, Super-H PFC, ABx500 and TZ1090. Support BIAS_BUS_HOLD,
get device tree parsing and debugfs support into shape.
- We also have device tree support with generic naming conventions
for the generic pin configuration.
- Delete the unused and confusing direct pinconf API. Now state
transitions is *the* way to control pins and multiplexing.
- New drivers for Rockchip, TZ1090, and TZ1090 PDC.
- Two pin control states related to power management are now
handled in the device core: "sleep" and "idle", removing a lot
of boilerplate code in drivers. We do not yet know if this is
the final word for pin PM, but it already make things a lot
easier to handle.
- Handle sparse GPIO ranges passing a list of disparate pins, and
utilize these in the new BayTrail (x86 Atom SoC) driver.
- Make the sunxi (AllWinner) driver handle external interrupts.
- Make it possible for pinctrl-single to handle the case where
several pins are managed by a single register, and augment it to
handle sleep modes.
- Cleanups and improvements for the abx500 drivers.
- Move Sirf pin control drivers to their own directory, support
save/restore of context and add support for the SiRFatlas6 SoC.
- PMU muxing for the Dove pinctrl driver.
- Finalization and support for VF610 in the i.MX6 pinctrl driver.
- Smoothen out various Exynos rough edges.
- Generic cleanups of various kinds.
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Merge tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
- A large slew of improvements of the Genric pin configuration support,
and deployment in four different platforms: Rockchip, Super-H PFC,
ABx500 and TZ1090. Support BIAS_BUS_HOLD, get device tree parsing
and debugfs support into shape.
- We also have device tree support with generic naming conventions for
the generic pin configuration.
- Delete the unused and confusing direct pinconf API. Now state
transitions is *the* way to control pins and multiplexing.
- New drivers for Rockchip, TZ1090, and TZ1090 PDC.
- Two pin control states related to power management are now handled in
the device core: "sleep" and "idle", removing a lot of boilerplate
code in drivers. We do not yet know if this is the final word for
pin PM, but it already make things a lot easier to handle.
- Handle sparse GPIO ranges passing a list of disparate pins, and
utilize these in the new BayTrail (x86 Atom SoC) driver.
- Make the sunxi (AllWinner) driver handle external interrupts.
- Make it possible for pinctrl-single to handle the case where several
pins are managed by a single register, and augment it to handle sleep
modes.
- Cleanups and improvements for the abx500 drivers.
- Move Sirf pin control drivers to their own directory, support
save/restore of context and add support for the SiRFatlas6 SoC.
- PMU muxing for the Dove pinctrl driver.
- Finalization and support for VF610 in the i.MX6 pinctrl driver.
- Smoothen out various Exynos rough edges.
- Generic cleanups of various kinds.
* tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe()
pinctrl: remove bindings for pinconf options needing more thought
pinctrl: remove slew-rate parameter from tz1090
pinctrl: set unit for debounce time pinconfig to usec
pinctrl: more clarifications for generic pull configs
pinctrl: rip out the direct pinconf API
pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver
pinctrl-tz1090: add TZ1090 pinctrl driver
pinctrl: samsung: Staticize drvdata_list
pinctrl: rockchip: Add missing irq_gc_unlock() call before return error
pinctrl: abx500: rework error path
pinctrl: abx500: suppress hardcoded value
pinctrl: abx500: factorize code
pinctrl: abx500: fix abx500_gpio_get()
pinctrl: abx500: fix abx500_pin_config_set()
pinctrl: abx500: Add device tree support
sh-pfc: Guard DT parsing with #ifdef CONFIG_OF
pinctrl: add Intel BayTrail GPIO/pinctrl support
pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc
pinctrl: Staticize local symbols
...
Conflicts:
drivers/net/ethernet/ti/davinci_mdio.c
drivers/pinctrl/Makefile
A small but useful set of regmap updates this time around:
- An abstraction for bitfields within a register map contributed by
Srinivas Kandagatla, allowing drivers to cope more easily when
hardware designers randomly move things about (mainly when talking
to things like system controllers).
- Changes from Lars-Peter Clausen to allow the MMIO regmap to be used from
hard IRQ context.
- Small improvements to the cache infrastructure and performance,
including a default cache sync operation so now all regmaps can sync
easily.
There's also a pinctrl driver making use of the new bitfield API, merged
here for dependency reasons. There will be a simple add/add conflict
with the pinctrl tree as a result.
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Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown:
"A small but useful set of regmap updates this time around:
- An abstraction for bitfields within a register map contributed by
Srinivas Kandagatla, allowing drivers to cope more easily when
hardware designers randomly move things about (mainly when talking
to things like system controllers).
- Changes from Lars-Peter Clausen to allow the MMIO regmap to be used
from hard IRQ context.
- Small improvements to the cache infrastructure and performance,
including a default cache sync operation so now all regmaps can
sync easily.
There's also a pinctrl driver making use of the new bitfield API,
merged here for dependency reasons. There will be a simple add/add
conflict with the pinctrl tree as a result."
* tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap:
pinctrl: st: Remove unnecessary use of of_match_ptr macro
pinctrl: st: fix return value check
pinctrl: st: Add pinctrl and pinconf support.
regmap: debugfs: Suppress cache for partial register files
regmap: Add regmap_field APIs
regmap: core: Cache all registers by default when cache is enabled
regmap: Implemented default cache sync operation
regmap: Make regmap-mmio usable from atomic contexts
regmap: regcache: Fixup locking for custom lock callbacks
regmap: debugfs: Fix return from regmap_debugfs_get_dump_start
regmap: debugfs: Don't mark lockdep as broken due to debugfs write
regmap: rbtree: Use range information to allocate nodes
regmap: rbtree: Factor out node allocation
regmap: Make regmap_check_range_table() a public API
regmap: Add support for discarding parts of the register cache
These are changes that arrived a little late before the merge
window or that have multiple dependencies on previous branches
so they did not fit into one of the earlier ones. There
are 10 branches merged here, a total of 39 non-merge commits.
Contents are a mixed bag for the above reasons:
* Two new SoC platforms: ST microelectronics stixxxx and
the TI 'Nspire' graphing calculator. These should have
been in the 'soc' branch but were a little late
* Support for the Exynos 5420 variant in mach-exynos,
which is based on the other exynos branches to avoid
conflicts.
* Various small changes for sh-mobile, ux500 and davinci
* Common clk support for MSM
Conflicts:
* In Kconfig.debug, various additions trivially conflict,
the list should be kept in alphabetical order when
resolving.
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Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Arnd Bergmann:
"These are changes that arrived a little late before the merge window
or that have multiple dependencies on previous branches so they did
not fit into one of the earlier ones. There are 10 branches merged
here, a total of 39 non-merge commits. Contents are a mixed bag for
the above reasons:
* Two new SoC platforms: ST microelectronics stixxxx and the TI
'Nspire' graphing calculator. These should have been in the 'soc'
branch but were a little late
* Support for the Exynos 5420 variant in mach-exynos, which is based
on the other exynos branches to avoid conflicts.
* Various small changes for sh-mobile, ux500 and davinci
* Common clk support for MSM"
* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
ARM: ux500: bail out on alien cpus
ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins
serial: sh-sci: Initialise variables before access in sci_set_termios()
ARM: stih41x: Add B2020 board support
ARM: stih41x: Add B2000 board support
ARM: sti: Add DEBUG_LL console support
ARM: sti: Add STiH416 SOC support
ARM: sti: Add STiH415 SOC support
ARM: msm: Migrate to common clock framework
ARM: msm: Make proc_comm clock control into a platform driver
ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver
ARM: msm: Remove clock-7x30.h include file
ARM: msm: Remove custom clk_set_{max,min}_rate() API
ARM: msm: Remove custom clk_set_flags() API
msm: iommu: Use clk_set_rate() instead of clk_set_min_rate()
msm: iommu: Convert to clk_prepare/unprepare
msm_sdcc: Convert to clk_prepare/unprepare
usb: otg: msm: Convert to clk_prepare/unprepare
msm_serial: Use devm_clk_get() and properly return errors
msm_serial: Convert to clk_prepare/unprepare
...
These changes are all driver specific and cross over between arm-soc
contents and some other subsystem, in these cases cpufreq, crypto,
dma, pinctrl, mailbox and usb, and the subsystem owners agreed to
have these changes merged through arm-soc. As we proceed to untangle
the dependencies between platform code and driver code, the amount of
changes in this category is fortunately shrinking, for 3.11 we have
16 branches here and 101 non-merge changesets, the majority of which
are for the stedma40 dma engine driver used in the ux500 platform.
Cleaning up that code touches multiple subsystems, but gets rid
of the dependency in the end.
The mailbox code moved out from mach-omap2 to drivers/mailbox
is an intermediate step and is still omap specific at the moment.
Patches exist to generalize the subsystem and add other drivers
with the same API, but those did not make it for 3.11.
Conflicts:
* In cpu-db8500.c results from the removal of the u8500_of_init_devices
function in combination with the split of u8500_auxdata_lookup.
* In arch/arm/mach-omap2/devices.c, the includes got reshuffled.
we need to keep linux/wl12xx.h and linux/platform_data/mailbox-omap.h.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann:
"These changes are all driver specific and cross over between arm-soc
contents and some other subsystem, in these cases cpufreq, crypto,
dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have
these changes merged through arm-soc.
As we proceed to untangle the dependencies between platform code and
driver code, the amount of changes in this category is fortunately
shrinking, for 3.11 we have 16 branches here and 101 non-merge
changesets, the majority of which are for the stedma40 dma engine
driver used in the ux500 platform. Cleaning up that code touches
multiple subsystems, but gets rid of the dependency in the end.
The mailbox code moved out from mach-omap2 to drivers/mailbox is an
intermediate step and is still omap specific at the moment. Patches
exist to generalize the subsystem and add other drivers with the same
API, but those did not make it for 3.11."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
crypto: ux500: use dmaengine_submit API
crypto: ux500: use dmaengine_prep_slave_sg API
crypto: ux500: use dmaengine_device_control API
crypto: ux500/crypt: add missing __iomem qualifiers
crypto: ux500/hash: add missing static qualifiers
crypto: ux500/hash: use readl on iomem addresses
dmaengine: ste_dma40: Declare memcpy config as static
ARM: ux500: Remove mop500_snowball_ethernet_clock_enable()
ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO
ARM: ux500: Provide a AB8500 GPIO Device Tree node
gpio: rcar: fix gpio_rcar_of_table
gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections
gpio-rcar: Reference core gpio documentation in the DT bindings
clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
ARM: dts: Update Samsung I2S documentation
ARM: dts: add clock provider information for i2s controllers in Exynos5250
ARM: dts: add Exynos audio subsystem clock controller node
clk: samsung: register audio subsystem clocks using common clock framework
ARM: dts: use #include for all device trees for Samsung
pinctrl: s3c24xx: use correct header for chained_irq functions
...
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Some options currently take arguments in unspecified driver-specific units.
As pointed out by Stephen Warren, driver specific values should not be part
of generic devicetree bindings describing the hardware.
Therefore remove the critical bindings again, before they become part of
an official release.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As the binding for slew-rate is under discussion and seems to need
more tought it will get removed for now, so it doesn't get an offical
release.
Therefore remove it again from the only current user, tz1090.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently the debounce time pinconfig option uses an unspecified
"time units" unit. As pinconfig options should use SI units and a
real unit is also necessary for generic dt bindings, change it
to usec. Currently no driver is using the generic pinconfig option
for this, so the unit change is safe to do.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PULL_PIN_DEFAULT is meant for hardware completely hiding any pull
settings from the driver, so that it's really only possible to turn
the pull on or off, but it not being possible to determine any
pull settings from software.
Also the binding-documentation for the pull arguments did not match
the changes to the expected values.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.
These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).
The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
ir_mod_stable_out and ir_mod_power_out functions respectively. If no
function is set they remain in GPIO mode. These muxes can be overridden
by requesting them as GPIOs.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We use the same way to define pin muxing and pin configuration
than for nomadik. So pickup code from pinctrl_nomadik.c to be
able to implement pin multiplexing and pin configuration using
the device tree. Pin configuration uses generic parsing code.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- enable RTC on exynos5250 snow and Arndale boards
- add support LCD and PWM for exynos4210 Origen board
- update bootargs to support 8GiB for exynos5440 SSDK5440 and SD5v1 boards
- enable spi and add opp level for exynos5440
- add example doc for samsung-pinctrl dt bindings
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Merge tag 'exynos-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
2nd exynos dt update based on tags/exynos-dt-1
- enable RTC on exynos5250 snow and Arndale boards
- add support LCD and PWM for exynos4210 Origen board
- update bootargs to support 8GiB for exynos5440 SSDK5440 and SD5v1 boards
- enable spi and add opp level for exynos5440
- add example doc for samsung-pinctrl dt bindings
* tag 'exynos-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Set BUCK7 as always on for Origen board
ARM: dts: Add FIMD node to Origen4210 board
ARM: dts: Add LCD related pinctrl entries for exynos4210
ARM: dts: Add PWM related pinctrl entries for exynos4210
Documentation: Add examples to samsung-pinctrl device tree bindings documentation
ARM: dts: Enable RTC node for exynos5250-snow
ARM: dts: Enable RTC node for Arndale
ARM: dts: Removing pdma for exynos5440
ARM: dts: update bootargs to support 8GiB for SSDK5440 and SD5v1
ARM: dts: Add more opp levels in exynos5440
ARM: dts: Add wm8994 regulator support on smdk5250
ARM: dts: enable spi for EXYNOS5440 SOC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Samsung EXYNOS5420 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5420.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by : Sunil Joshi <joshi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.
Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds examples to samsung-pinctrl.txt documentaion file
on how to make gpio binding and gpio request
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The bias-pull-* options use values > 0 to indicate that the pull should
be activated and optionally also indicate the strength of the pull.
Therefore use an default value of 1 for these options.
Split the low-power-mode option into low-power-enable and -disable.
Update the documentation to describe the param arguments better.
Reported-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
With the commit 7f217794f (mmc: dt: Consolidate DT bindings),
the device tree properties used by various device drivers
for SD/MMC host controllers were standardized. One of the changes
was that the property "fsl,card-wired", previously used by the
Freescale driver, was replaced with "non-removable". Fix the example
documentation regarding this.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.
Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinconf_generic_parse_dt_config() takes a node as input and generates an
array of generic pinconfig values from the properties of this node.
As I couldn't find a mechanism to count the number of properties of a node
the function uses internally an array to accept one of parameter and copies
the real present options to a smaller variable at its end.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a),
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dove power management unit can mux some special functions to mpp0-15.
This patch adds support to set/get the current PMU function mapped
to the corresponding mpp pins. The device tree documentation is also
updated accordingly.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.
The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.
Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
These are mostly new device tree bindings for existing drivers, as well
as changes to the device tree source files to add support for those
devices, and a couple of new boards, most notably Samsung's Exynos5
based Chromebook.
The changes depend on earlier platform specific updates and touch
the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci.
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Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates (part 2) from Arnd Bergmann:
"These are mostly new device tree bindings for existing drivers, as
well as changes to the device tree source files to add support for
those devices, and a couple of new boards, most notably Samsung's
Exynos5 based Chromebook.
The changes depend on earlier platform specific updates and touch the
usual platforms: omap, exynos, tegra, mxs, mvebu and davinci."
* tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: exynos: dts: cros5250: add EC device
ARM: dts: Add sbs-battery for exynos5250-snow
ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
ARM: dts: add mshc controller node for Exynos4x12 SoCs
ARM: dts: Add chip-id controller node on Exynos4/5 SoC
ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
ARM: davinci: da850-evm: add SPI flash support
ARM: davinci: da850: override SPI DT node device name
ARM: davinci: da850: add SPI1 DT node
spi/davinci: add DT binding documentation
spi/davinci: no wildcards in DT compatible property
ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
ARM: dts: mvebu: introduce internal-regs node
ARM: dts: mvebu: Convert all the mvebu files to use the range property
ARM: dts: mvebu: move all peripherals inside soc
ARM: dts: mvebu: fix cpus section indentation
ARM: davinci: da850: add EHRPWM & ECAP DT node
ARM/dts: OMAP3: fix pinctrl-single configuration
ARM: dts: Add OMAP3430 SDP NOR flash memory binding
ARM: dts: Add NOR flash bindings for OMAP2420 H4
...
This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem
specific interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into
platform specific interface, or to get called from platform specific
code, as long as all information about the hardware is provided
through a device tree.
Most of the drivers we touch this time are for clocksource. Since
now most of them are part of drivers/clocksource, I expect that we
won't have to touch these again from arm-soc and can let the
clocksource maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the
merge conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface
for taking devices on the SoC out of reset or back into reset.
Patches to use this interface on i.MX follow later in this merge
window, and we are going to have other platforms (at least tegra
and sirf) get converted in 3.11. This will let us get rid of
platform specific callbacks in a number of platform independent
device drivers.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.
Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
Device-tree updates for 3.10. The bulk of the churn in this branch is due
to i.MX moving from C-defined pin control over to device tree, which is
a one-time conversion that will allow greater flexibility down the road.
Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
handful of cleanups to tegra due to the new include file functionality
of the device tree compiler.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree updates from Olof Johansson:
"Part 1 of device-tree updates for 3.10. The bulk of the churn in this
branch is due to i.MX moving from C-defined pin control over to device
tree, which is a one-time conversion that will allow greater
flexibility down the road.
Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
handful of cleanups to tegra due to the new include file functionality
of the device tree compiler"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits)
arm: mvebu: PCIe Device Tree informations for Armada XP GP
arm: mvebu: PCIe Device Tree informations for Armada 370 DB
arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
arm: mvebu: PCIe Device Tree informations for Armada XP DB
arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
arm: mvebu: add PCIe Device Tree informations for Armada XP
arm: mvebu: add PCIe Device Tree informations for Armada 370
ARM: sunxi: unify osc24M_fixed and osc24M
arm: vt8500: Add SDHC support to WM8505 DT
ARM: dts: Add a 64 bits version of the skeleton device tree
ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
ARM: dts: imx6dl-wandboard: Add USB Host support
ARM: dts: imx51 cpu node
ARM: dts: Add missing imx27-phytec-phycore dtb target
ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
ARM: i.MX51: Add PATA support
ARM: dts: Add initial support for Wandboard Dual-Lite
...
Add a pinctrl driver for i.MX6 SoloLite based on pinctrl-imx core
driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The imx6dl is a derivative of imx6q with very limited difference. These
two SoCs are so compatible that they can be handled as one platform in
software. That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q. That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some pins on the i.mx23 and i.mx28 are missing pull-ups, document that
oddity because it was difficult to know the expected behaviour.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.
Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.
All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add comments with pinconf & gpio range in the document of
pinctrl-single.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bug fixes that did not make it into v3.8, mostly because they were not
considered important enough, and in some cases because bugs only show
up in combination with other patches destined for 3.9.
This includes a few larger patches for GPIO on the Marvell PXA platform
and a lot of Samsung specific bug fixes, as well as a series from Arnd
to fix older build warnings.
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Merge tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull non-critical ARM SoC bug fixes from Arnd Bergmann:
"Bug fixes that did not make it into v3.8, mostly because they were not
considered important enough, and in some cases because bugs only show
up in combination with other patches destined for 3.9. This includes
a few larger patches for GPIO on the Marvell PXA platform and a lot of
Samsung specific bug fixes, as well as a series from Arnd to fix older
build warnings."
* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
ARM: SPEAr13xx: Enable CONFIG_ARCH_HAS_CPUFREQ
ARM: imx: MACH_MX31ADS_WM1133_EV1 needs REGULATOR_WM8350
scripts/sortextable: silence script output
ARM: s3c: i2c: add platform_device forward declaration
ARM: mvebu: allow selecting mvebu without Armada XP
ARM: pick Versatile by default for !MMU
ARM: integrator: fix build with INTEGRATOR_AP off
ARM: integrator/versatile: fix NOMMU warnings
ARM: sa1100: don't warn about mach/ide.h
ARM: shmobile: fix defconfig warning on CONFIG_USB
ARM: w90x900: fix legacy assembly syntax
ARM: samsung: fix assembly syntax for new gas
ARM: disable virt_to_bus/virt_to_bus almost everywhere
ARM: dts: Correct pin configuration of SD 4 for exynos4x12-pinctrl
ARM: SAMSUNG: Silence empty switch warning in fimc-core.h
ARM: SAMSUNG: Silence empty switch warning in sdhci.h
ARM: msm: proc_comm_boot_wait should not be __init
arm: vt8500: Update MAINTAINERS entry for arch-vt8500
ARM: integrator: ensure ap_syscon_base is initialised when !CONFIG_MMU
ARM: S5PV210: Fix early uart output in fifo mode
...
- Grabbing of default pinctrl handles from the device core.
These are the hunks hitting drivers/base. All is ACKed by
Greg, after a long discussion about different alternatives.
- Some stuff also touches the MFD and ARM SoC trees, this has
been coordinated and ACKed.
- New drivers for:
- The Tegra 114 sub-SoC
- Allwinner sunxi
- New ABx500 driver and sub-SoC drivers for AB8500,
AB8505, AB9540 and AB8540.
- Make it possible for hogged pins to enter a sleep mode,
and make it possible for drivers to control that mode.
- Various clean-up, extensions and device tree support to
various pin controllers.
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Merge tag 'pinctrl-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl changes from Linus Walleij:
"These are the main pinctrl changes for the v3.9 merge window. The
most interesting change by far is how the device core grabs pinctrl
default handles avoiding the need to stick boilerplate into driver
consumers.
- Grabbing of default pinctrl handles from the device core. These
are the hunks hitting drivers/base. All is ACKed by Greg, after a
long discussion about different alternatives.
- Some stuff also touches the MFD and ARM SoC trees, this has been
coordinated and ACKed.
- New drivers for:
- The Tegra 114 sub-SoC
- Allwinner sunxi
- New ABx500 driver and sub-SoC drivers for AB8500, AB8505, AB9540
and AB8540.
- Make it possible for hogged pins to enter a sleep mode, and make it
possible for drivers to control that mode.
- Various clean-up, extensions and device tree support to various pin
controllers."
* tag 'pinctrl-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (68 commits)
pinctrl: tegra: add clfvs function to Tegra114 support
pinctrl: generic: rename input schmitt disable
pinctrl/pinconfig: add debug interface
pinctrl: samsung: remove duplicated line
ARM: ux500: use real AB8500 IRQ numbers instead of virtual ones
ARM: ux500: remove irq_base property from platform_data
pinctrl/abx500: use direct IRQ defines
pinctrl/abx500: replace IRQ offsets with table read-in values
pinctrl/abx500: move IRQ handling to ab8500-core
pinctrl: exynos5440: remove erroneous __init
pinctrl/abx500: adjust offset for get_mode()
pinctrl/abx500: add Device Tree support
pinctrl/abx500: align GPIO cluster boundaries
pinctrl/abx500: prevent error path from corrupting returning error
pinctrl: sunxi: add of_xlate function
pinctrl/lantiq: fix pin number in ltq_pmx_gpio_request_enable
pinctrl/lantiq: add functionality to falcon_pinconf_dbg_show
pinctrl/lantiq: fix pinconfig parameters
pinctrl/lantiq: one of the boot leds was defined incorrectly
pinctrl/lantiq: only probe available pad controllers
...
Fix the incorrect compatible property value of pinctrl for EXYNOS4 SoCs.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The relation between PIN_BANK numbers and pio letters wasn't made very
clear.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.
This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.
This driver only implements the pinctrl part, the gpio part will come
eventually.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.
The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.
This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".
Originally written by Pritesh.
ldewangan:
- cleanup the patches,
- remove non-require tables.
- Use module_platform_driver() for driver registartion.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This implements pin multiplexing and pin configuration for
the Nomadik pin controller using the device tree.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@stericsson.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jacopo Mondi
Linus Walleij
Chen-Yu Tsai
Icenowy Zheng
Paul Cercueil
Shawn Guo
Sergei Shtylyov
Colin Ian King
Andrew Jeffery
Alexandre TORGUE
Gregory CLEMENT
Jesper Nilsson
Andy Yan
Icenowy Zheng
david.wu
Masahiro Yamada
Kalyan Kinthada
Marek Szyprowski
Fabio Estevam
Nishanth Menon
Andreas Klinger
Linus Torvalds
David Lechner
Keerthy
Peter Rosin
Olof Johansson
Maxime Ripard
Chanwoo Choi
Andrey Smirnov
Tony Lindgren
Michael Scott
Neil Armstrong
Boris BREZILLON
Jamie Lentin
Krzysztof Kozlowski
Peter Griffin
Mylène Josserand
Takeshi Kihara
Patrice Chotard
Stephen Boyd
Ray Jui
Jon Hunter
Stephen Boyd
Yendapally Reddy Dhananjaya Reddy
Wolfram Sang
Carlo Caione
Laxman Dewangan
Purna Chandra Mandal
Arnd Bergmann
Thierry Reding
Eric Engestrom
Govindraj Raja
Laurent Pinchart
Andre Przywara
Joachim Eastwood
Krzysztof Adamski
John Crispin
Varadarajan Narayanan
Joshua Henderson
Maxime Coquelin
Biao Huang
Jeffy Chen
Jens Kuske
Yendapally Reddy Dhananjaya Reddy
Joonwoo Park
Martin Schiller
Pramod Kumar
Hakjoo Kim
Jisheng Zhang
Adrian Alonso
Vishnu Patekar
Ludovic Desroches
Ben Hutchings
Frank Li
Baruch Siach
Bjorn Andersson
Thomas Langer
Heiko Stübner
Hisashi Nakamura
Kevin Hilman
Thomas Petazzoni
Wei Chen
Hongzhou Yang
Antoine Tenart
Ulrich Hecht
Helmut Buchsbaum
Andrew Bresticker
Ivan T. Ivanov
Ray Jui
Stephen Warren
Paul Walmsley
Stanimir Varbanov
Magnus Damm
Niklas Söderlund
Padmavathi Venna
Hans de Goede
Vivek Gautam
Soren Brinkmann
Beniamino Galvani
James Hogan
Naveen Krishna Ch
Abhilash Kesavan
Yingjoe Chen
Ivan T. Ivanov
Sean Paul
Marek Roszko
Georgi Djakov
Pramod Gurav
Doug Anderson
Geert Uytterhoeven
Tomasz Figa
Andy Gross
Anson Huang
Carlos Garcia
Boris BREZILLON
Sherman Yin
Jason Cooper
Sebastian Hesselbarth
Young-Gun Jang
Chao Xie
Srinivas Kandagatla
Tomi Valkeinen
Denis Carikli
Markus Pargmann
Christian Ruppert
Lothar Waßmann
Mateusz Krawczuk
Lee Jones
Masanari Iida
Leela Krishna Amudala
Dirk Behme
Manjunathappa, Prakash
Jingchang Lu
Lad, Prabhakar
Tomasz Figa
Alexandre Belloni
Tony Prisk
Haojian Zhuang
Kukjin Kim
Richard Genoud
Pritesh Raithatha
Gabriel Fernandez